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Vitis Custom Embedded Platform Creation Example on ZCU104 DPU Test 3: Run a Vitis-AI Demo not working #122
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The |
I went through all 4 steps of the tutorial again without changing anything. The only change was that I used Vitis AI branch 1.3.2 instead of V1.3 and still the results are incorrect. This is getting really frustrating for me because I'm doing exactly what the tutorial tells me to do, I don't even get any errors but the model is not giving proper outputs. |
The v++ configuration settings is set by https://github.com/Xilinx/Vitis-AI/blob/v1.3/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_gui and this file is associated to the application project by https://github.com/Xilinx/Vitis-AI/blob/v1.3/dsa/DPU-TRD/description.json In
If you update the description.json, it can be something like this:
I have reported this issue before but the fix hasn't been applied yet. Sorry for this gap in the tutorial. |
Hi @imrickysu, Thanks for the answer, I really appreciate your quick answers to my comments. But even with having zcu104_base in the platform's name, the resnet from the application project on my custom platform is not working.
I'm really frustrated at this moment after running this tutorial on many different conditions several times, so please tell me if you have any idea why the model may not work. Or a way to debug the DPU cores' behavior. Obviously this tutorial has not been tested on the current version of Vitis and Vitis AI, so please test it, find the issues and update the tutorial. |
Hi @Ali-Flt , I reran the VAI test for 2020.2. It worked well on my side. Could you try to create the Vitis-AI application with the platform generated by the Makefile ? You can run For the configuration setting issue we discussed above, the tutorial Step 5 (Update system_hw_link for proper kernel instantiation) considered this issue and provided the method to overcome the descrption.json setting specific the platform name. |
Hi @imrickysu , So after that I went to the make scripts in each step and looked for differences with the tutorial. Please read the differences I found and update the tutorial, because one of them is probably the cause of the platform not working.
I couldn't find any other differences but I may have missed something. I also didn't check the PS's configurations for any mismatch. Step 2:
(Note that the rootfs configs were different too but I believe the problem is not hidden in the rootfs because I ran the test with my own generated rootfs without issues so I didn't mention the rootfs differences.) Step 3: I did the last step (running the Vitis AI demo) exactly like before in the GUI so either the error lies in the things I mentioned above, or the behavior of VIVADO/Vitis GUI flow is not as expected and is not the same as the VIVADO/xsct script flow. Thanks again for solving the issue for me by your suggestion and I hope this info helps in finding and fixing the issue in the tutorial. |
2021.1 next
f7d1abc Merge pull request Xilinx#122 from tuol/disable_2_case ae62691 disable 2 case due to U250 platform change 3af143e Merge pull request Xilinx#118 from tuol/fix_cr_1122542 3e7f919 temporally disable L3/tests/mlp, due to U250 platform change 1728d13 update opts.cfg 98d3f3f Merge pull request Xilinx#117 from yuanqian/next 8639708 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 18a7458 Merge pull request Xilinx#116 from changg/wa_u280_201920 86e28ef WA for xilinx_u280_xdma_201920_3 07abe54 Merge pull request Xilinx#114 from liyuanz/replace_cflags 7cb157c replace cflags with clflags 0196ded Merge pull request Xilinx#113 from changg/cov_fix fc100b4 cov fix b201f43 cov fix 14067e6 Merge pull request Xilinx#110 from liyuanz/next bbe42e9 fix bug 257677d Merge pull request Xilinx#109 from changg/pr_108 79db50c fix makefiles 984a71c update Makefile and utils daf9820 Merge pull request Xilinx#106 from liyuanz/replace_blacklist 28fe2ed replace whiltelist/blacklist to allowlist/blocklist 981b5a2 Merge pull request Xilinx#105 from changg/pr_104 2f45a63 add time for hw_build a21b8db add time 7256e35 add time 5f2c36a Merge pull request Xilinx#102 from changg/add_extraflags acce305 fix utils.mk 74536af fix utils.mk 3c0647e Merge pull request Xilinx#101 from liyuanz/next fc26744 increase mem 7a1b220 Merge pull request Xilinx#99 from changg/fix_mks 055c521 fix typ 44ff7b9 fix utils.mk 4050d17 Merge pull request Xilinx#98 from liyuanz/replace_targets b0157d6 update targes e41fc60 Merge pull request Xilinx#96 from changg/metadata f6d1e26 draft metadata 0bbb982 change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <[email protected]>
cf4065d Merge pull request Xilinx#123 from RepoOps/update_readme_5 4890779 update README fa29498 update README 61c2cb5 Merge pull request Xilinx#119 from RepoOps/update_doc_url_3 b871455 fix url 2f7fb05 Merge pull request Xilinx#122 from tuol/cr_1142093_2 59cf572 fix input of cscmv de579fa Merge pull request Xilinx#121 from tuol/cr_1140416 c00a509 update makefile and description.json for L2_tests_fp64_spmv 0a0771e update url and branch in doc a69541e Merge pull request Xilinx#118 from tuol/fix_version dfc5cb7 update version to 2022.2 Co-authored-by: sdausr <[email protected]>
Closing the thread as there are no open concerns. Thanks |
Hi, I've gone through this tutorial with Vitis 2020.2 and Vitis AI v1.3 : https://github.com/Xilinx/Vitis-Tutorials/tree/2020.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104
With some slight differences:
git clone https://github.com/Xilinx/Vitis-AI.git
git checkout v1.3
And added the repo to vitis like this:
Every other step and instruction was followed without error.
But when I run the Vitis-AI demo on the bell pepper image, I get this for the first run:
Notice there are some errors that I have no idea about the reason:
And I get this results for the runs after the first one:
As you can see the app runs without errors but the predictions are not correct at all.
Any ideas why this could happen or how I can debug this?
Thanks
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