Pre-synthesis Control Flow Error occurred after running C simulation #121
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Same problem reported on Xilinx forum, but not solved. |
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Can you post your operating system information here? |
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vmayoral
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Jan 20, 2022
2021.1 next
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Hi all, Is there any update regarding this issue? I am having the same problem in Vitis HLS 2020.2 on Ubuntu 20.04.6 LTS. |
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The issue appears to be something related to the environment or system setup. I was not able to recreate the problem described above. Can you share any additional information related to your environment? |
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Hi again and thank you for the quick reply! Actually i found the problem in my case. There was a problem with my setup. I had to change my default desktop environment with this command "$ sudo update-alternatives --config x-session-manager". |
CRTejaswi
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Oct 3, 2023
cf4065d Merge pull request Xilinx#123 from RepoOps/update_readme_5 4890779 update README fa29498 update README 61c2cb5 Merge pull request Xilinx#119 from RepoOps/update_doc_url_3 b871455 fix url 2f7fb05 Merge pull request Xilinx#122 from tuol/cr_1142093_2 59cf572 fix input of cscmv de579fa Merge pull request Xilinx#121 from tuol/cr_1140416 c00a509 update makefile and description.json for L2_tests_fp64_spmv 0a0771e update url and branch in doc a69541e Merge pull request Xilinx#118 from tuol/fix_version dfc5cb7 update version to 2022.2 Co-authored-by: sdausr <[email protected]>
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After I ran the C simulation on the synthesis and analysis part of the Vitis HLS Getting Started tutorial, the dct_csim.log gave TEST PASSED, but the Pre-synthesis control flow did not show up and an error occurred in the problem console as the followings:
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