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corrected path for git clone #123

Merged
merged 1 commit into from
Nov 6, 2021
Merged

corrected path for git clone #123

merged 1 commit into from
Nov 6, 2021

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randyh62
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@randyh62 randyh62 commented Nov 5, 2021

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@imrickysu imrickysu merged commit 7486a4f into Xilinx:2021.1 Nov 6, 2021
imrickysu pushed a commit that referenced this pull request Dec 3, 2021
vmayoral pushed a commit to vmayoral/Vitis-Tutorials that referenced this pull request Jan 20, 2022
Versal Platform Creation Tutorial update
imrickysu pushed a commit that referenced this pull request Nov 3, 2022
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this pull request Oct 3, 2023
2079b9b Ethash SC prototype (Xilinx#150)
c08ada1 merge tutorial (Xilinx#157)
04302db Merge pull request Xilinx#155 from changg/fix_issues
f792a67 revert the change
98ccdea test
8fa693a fix security issues
f60f3c8 Update Makefile (Xilinx#152)
9612886 Fix cr 1114888 1114873 (Xilinx#151)
e622384 update rc4 benchmark case, reduce to 1 kernel (Xilinx#149)
8b43251 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 (Xilinx#145)
3d86755 Fix cr 1114880 1114888 (Xilinx#146)
49d5003 Merge pull request Xilinx#144 from liyuanz/replace_cflags
43651c8 replace cflags with clflags
ee65b70 Add open file failure guard and mode for read-only (Xilinx#143)
a05e213 Merge pull request Xilinx#141 from liyuanz/replace_blacklist
9095130 replace whiltelist/blacklist to allowlist/blocklist
fb7dfd6 Merge pull request Xilinx#137 from leol/fix-CR
4454482 Merge pull request Xilinx#138 from liyuanz/next
ded8552 add mem for mem limit case
80dddf9 Fix for L1 CBC SC benchmarks host build issue
dd68b83 Clang format crc32c_sc.cpp with 3.9.0 version
443fa59 Merge pull request Xilinx#132 from liyuanz/next
34bc727 Merge pull request Xilinx#134 from liyuanz/replace_targets
be250a9 update targes
3e28567 update
e0cbc3d Refine crc32c to improve the performance of the resdu line (Xilinx#133)
884b4f9 update
c790abe update
0256aac update
61cb658 update Makefile and utils.mk
359c5b6 Clang format crc32c_sc.cpp for both 3.9.0 and 8.0.0 (Xilinx#131)
92cf068 SC L3 design of CRC32C (Xilinx#123)
c00352b update Makefile for Vitis Flow testcase (Xilinx#128)
33c3c23 remove ssl linkage from library,json (Xilinx#127)
c67da48 Merge pull request Xilinx#126 from changg/metadata
080686b draft metadata files
e3efd4d add aws support (Xilinx#124)
87f65b0 change 2021.2_stable_latest to 2022.1_stable_latest

Co-authored-by: sdausr <[email protected]>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this pull request Oct 3, 2023
cf4065d Merge pull request Xilinx#123 from RepoOps/update_readme_5
4890779 update README
fa29498 update README
61c2cb5 Merge pull request Xilinx#119 from RepoOps/update_doc_url_3
b871455 fix url
2f7fb05 Merge pull request Xilinx#122 from tuol/cr_1142093_2
59cf572 fix input of cscmv
de579fa Merge pull request Xilinx#121 from tuol/cr_1140416
c00a509 update makefile and description.json for L2_tests_fp64_spmv
0a0771e update url and branch in doc
a69541e Merge pull request Xilinx#118 from tuol/fix_version
dfc5cb7 update version to 2022.2

Co-authored-by: sdausr <[email protected]>
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2 participants