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Tutorial vadd on sw_emu using xilinx_u250_gen3x16_xdma_3_1_202020_1 caused error in ./app.exe #105

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danna2019 opened this issue Sep 8, 2021 · 1 comment

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@danna2019
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On the tutorial "Getting Started: Part4/Instructions for the Alveo U200 platform", I'd like to use Alveo U250, installed some platform dependent files on "/opt/xilinx/platforms/xilinx_u250_gen3x16_xdma_3_1_202020_1", and "Vitis-Tutorials/Getting_Started/Vitis/example/src/u200.conf" to u250.conf as below:

platform=xilinx_u250_gen3x16_xdma_3_1_202020_1
debug=1
save-temps=1

[connectivity]
nk=vadd:1:vadd_1
sp=vadd_1.in1:DDR[1]
sp=vadd_1.in2:DDR[2]
sp=vadd_1.out:DDR[1]

[profile]
data=all:all:all

and some commands following the instruction as:

$ g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++
$ emconfigutil --platform xilinx_u250_gen3x16_xdma_3_1_202020_1 --nd 1
$ v++ -c -t sw_emu --config ../../src/u250.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo
$ v++ -l -t sw_emu --config ../../src/u250.cfg ./vadd.xo -o vadd.xclbin

after the instruction, I've try to "./app.exe". Unfortunately it's occurred 'Segmentation fault'.

$ export XCL_EMULATION_MODE=sw_emu
$ ./app.exe 
INFO: Found Xilinx Platform
INFO: Loading 'vadd.xclbin'
terminate called after throwing an instance of '__gnu_cxx::recursive_init_error'
  what():  std::exception
Segmentation fault (core dumped)

How I should be?

@danna2019
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Self solved.

CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
bf99958 update conf.py for release version and add release note (Xilinx#105)
47283e6 add description in description.json (Xilinx#103)
4b98198 add crc32c (Xilinx#88)
f89c4fd change doc format, and include guard name (Xilinx#102)
a7a98cc optimize adler32's timing (Xilinx#90)

Co-authored-by: sdausr <[email protected]>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
f7d1abc Merge pull request Xilinx#122 from tuol/disable_2_case
ae62691 disable 2 case due to U250 platform change
3af143e Merge pull request Xilinx#118 from tuol/fix_cr_1122542
3e7f919 temporally disable L3/tests/mlp, due to U250 platform change
1728d13 update opts.cfg
98d3f3f Merge pull request Xilinx#117 from yuanqian/next
8639708 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831
18a7458 Merge pull request Xilinx#116 from changg/wa_u280_201920
86e28ef WA for xilinx_u280_xdma_201920_3
07abe54 Merge pull request Xilinx#114 from liyuanz/replace_cflags
7cb157c replace cflags with clflags
0196ded Merge pull request Xilinx#113 from changg/cov_fix
fc100b4 cov fix
b201f43 cov fix
14067e6 Merge pull request Xilinx#110 from liyuanz/next
bbe42e9 fix bug
257677d Merge pull request Xilinx#109 from changg/pr_108
79db50c fix makefiles
984a71c update Makefile and utils
daf9820 Merge pull request Xilinx#106 from liyuanz/replace_blacklist
28fe2ed replace whiltelist/blacklist to allowlist/blocklist
981b5a2 Merge pull request Xilinx#105 from changg/pr_104
2f45a63 add time for hw_build
a21b8db add time
7256e35 add time
5f2c36a Merge pull request Xilinx#102 from changg/add_extraflags
acce305 fix utils.mk
74536af fix utils.mk
3c0647e Merge pull request Xilinx#101 from liyuanz/next
fc26744 increase mem
7a1b220 Merge pull request Xilinx#99 from changg/fix_mks
055c521 fix typ
44ff7b9 fix utils.mk
4050d17 Merge pull request Xilinx#98 from liyuanz/replace_targets
b0157d6 update targes
e41fc60 Merge pull request Xilinx#96 from changg/metadata
f6d1e26 draft metadata
0bbb982 change 2021.2_stable_latest to 2022.1_stable_latest

Co-authored-by: sdausr <[email protected]>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
1b75f16 Merge pull request Xilinx#117 from liyuanz/add_m
cfc460f update
1b1fd0c Merge pull request Xilinx#116 from tuol/cr_1138695
990951d remove connectivity from opts.cfg
fcff114 Merge pull request Xilinx#112 from liyuanz/next
3c583c5 Merge branch 'next' into next
d148b7e Merge pull request Xilinx#115 from tuol/1135042_2
517ab80 fix description.json
875ee0b Merge pull request Xilinx#114 from tuol/cr_1135042_1
66a513b fix description.json
818c768 Merge pull request Xilinx#113 from tuol/cr_1138695
0dd07e2 add missing app.bin
246611d update mk
be55cf9 Merge pull request Xilinx#111 from tuol/cr_1138321_1
0a3d580 fix --nk option in connectivity setup
c48114c Merge pull request Xilinx#110 from tuol/cr_1138321
35c48bc fix makefile, description.json and connectivity setup of cscmv and cscmvSingleHBM
651be1e Merge pull request Xilinx#109 from tuol/cr_1135042
e4becb4 remove un-allowed properties from description.json
370087d Merge pull request Xilinx#107 from yuanqian/update_doc_next_portal
b4d95f0 Merge pull request Xilinx#108 from liyuanz/add_mem
5fb26ce add mem
90fb7b8 update
24b1d5e add memory
f454c44 update doc in next branch for portal
0ea11e4 Merge pull request Xilinx#105 from yuanqian/update_hls_pragma
3491287 Merge pull request Xilinx#106 from liyuanz/next
4c5d9a3 update
f81ca5a update hls pragma
ab89f67 change 2022.1_stable_latest to 2022.2_stable_latest
20d34e9 Merge pull request Xilinx#103 from tuol/fix_conf_py
5b45226 update conf.py
eb29003 Update Jenkinsfile

Co-authored-by: sdausr <[email protected]>
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