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07-AI-Engine-Floating-Point/MatMult/ AIE config JSON file missing #113
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@smitha-xilinx can you have someone take a look at this? |
The error on customer side seems to be in the aie compilation. Can we have more details on the AIE compilation error? |
The full log is below. It looks like the AIE is missing the config JSON file. Specifically: " AIE Simulator config Json file missing, file: Work/config/scsim_config.json" The environment is as below: Vivado 2021.1
Apart from that, I just issue make all under this directory.
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Hi, We can see at the end of the compilation the error: The problem comes from the way you defined the PLATFORM_REPO_PATH variable. It should be: This modification should solve the compilation stage, and the simulation should be able to run. |
Hi, I can confirm that works. Thank you , closing this. |
Add an optional description.json file.
Updated Makefiles for changes to regressions
Add an optional description.json file.
db743e9 updat url in README.md and doc (Xilinx#113) 5d6466a Revert "nistp256 draft (Xilinx#107)" (Xilinx#112) 1d98667 nistp256 draft (Xilinx#107) dec7844 Merge pull request Xilinx#109 from changg/test_timelimit 96f8c42 add memlimit Co-authored-by: sdausr <[email protected]>
f7d1abc Merge pull request Xilinx#122 from tuol/disable_2_case ae62691 disable 2 case due to U250 platform change 3af143e Merge pull request Xilinx#118 from tuol/fix_cr_1122542 3e7f919 temporally disable L3/tests/mlp, due to U250 platform change 1728d13 update opts.cfg 98d3f3f Merge pull request Xilinx#117 from yuanqian/next 8639708 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 18a7458 Merge pull request Xilinx#116 from changg/wa_u280_201920 86e28ef WA for xilinx_u280_xdma_201920_3 07abe54 Merge pull request Xilinx#114 from liyuanz/replace_cflags 7cb157c replace cflags with clflags 0196ded Merge pull request Xilinx#113 from changg/cov_fix fc100b4 cov fix b201f43 cov fix 14067e6 Merge pull request Xilinx#110 from liyuanz/next bbe42e9 fix bug 257677d Merge pull request Xilinx#109 from changg/pr_108 79db50c fix makefiles 984a71c update Makefile and utils daf9820 Merge pull request Xilinx#106 from liyuanz/replace_blacklist 28fe2ed replace whiltelist/blacklist to allowlist/blocklist 981b5a2 Merge pull request Xilinx#105 from changg/pr_104 2f45a63 add time for hw_build a21b8db add time 7256e35 add time 5f2c36a Merge pull request Xilinx#102 from changg/add_extraflags acce305 fix utils.mk 74536af fix utils.mk 3c0647e Merge pull request Xilinx#101 from liyuanz/next fc26744 increase mem 7a1b220 Merge pull request Xilinx#99 from changg/fix_mks 055c521 fix typ 44ff7b9 fix utils.mk 4050d17 Merge pull request Xilinx#98 from liyuanz/replace_targets b0157d6 update targes e41fc60 Merge pull request Xilinx#96 from changg/metadata f6d1e26 draft metadata 0bbb982 change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <[email protected]>
1b75f16 Merge pull request Xilinx#117 from liyuanz/add_m cfc460f update 1b1fd0c Merge pull request Xilinx#116 from tuol/cr_1138695 990951d remove connectivity from opts.cfg fcff114 Merge pull request Xilinx#112 from liyuanz/next 3c583c5 Merge branch 'next' into next d148b7e Merge pull request Xilinx#115 from tuol/1135042_2 517ab80 fix description.json 875ee0b Merge pull request Xilinx#114 from tuol/cr_1135042_1 66a513b fix description.json 818c768 Merge pull request Xilinx#113 from tuol/cr_1138695 0dd07e2 add missing app.bin 246611d update mk be55cf9 Merge pull request Xilinx#111 from tuol/cr_1138321_1 0a3d580 fix --nk option in connectivity setup c48114c Merge pull request Xilinx#110 from tuol/cr_1138321 35c48bc fix makefile, description.json and connectivity setup of cscmv and cscmvSingleHBM 651be1e Merge pull request Xilinx#109 from tuol/cr_1135042 e4becb4 remove un-allowed properties from description.json 370087d Merge pull request Xilinx#107 from yuanqian/update_doc_next_portal b4d95f0 Merge pull request Xilinx#108 from liyuanz/add_mem 5fb26ce add mem 90fb7b8 update 24b1d5e add memory f454c44 update doc in next branch for portal 0ea11e4 Merge pull request Xilinx#105 from yuanqian/update_hls_pragma 3491287 Merge pull request Xilinx#106 from liyuanz/next 4c5d9a3 update f81ca5a update hls pragma ab89f67 change 2022.1_stable_latest to 2022.2_stable_latest 20d34e9 Merge pull request Xilinx#103 from tuol/fix_conf_py 5b45226 update conf.py eb29003 Update Jenkinsfile Co-authored-by: sdausr <[email protected]>
Makefile:48: recipe for target 'aie' failed
make[1]: [aie] Error 255 (ignored)
if [ -f ../Module2.build.log ]; then cp ../Module2.build.log ./build.log 2>/dev/null; echo; echo "INFO: Look at the log file Debug/build.log for more details."; else echo "Warning: Build log file ../Module2.build.log doesn't exist."; fi; \
Warning: Build log file ../Module2.build.log doesn't exist.
if [ -d data ]; then echo "data exists"; else ln -s ../data data; fi;
aiesimulator --pkg-dir=Work --dump-vcd=foo
AIEsim feature license is found.
INFO: Executing config: Work/config/scsim_config.json
terminate called after throwing an instance of 'std::runtime_error'
what(): AIE Simulator config Json file missing, file: Work/config/scsim_config.json
/tools/Xilinx/Vitis/2021.1/aietools/bin/loader: line 312: 79090 Aborted (core dumped) "$RDI_PROG" "$@"
Makefile:52: recipe for target 'aiesim' failed
make[1]: *** [aiesim] Error 134
make[1]: Leaving directory '/home/dhq/Documents/Vitis-Tutorials/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/MatMult/Emulation-AIE'
Makefile:19: recipe for target 'all' failed
make: *** [all] Error 2
The text was updated successfully, but these errors were encountered: