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07-AI-Engine-Floating-Point/MatMult/ AIE config JSON file missing #113

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Q-point opened this issue Oct 11, 2021 · 5 comments
Closed

07-AI-Engine-Floating-Point/MatMult/ AIE config JSON file missing #113

Q-point opened this issue Oct 11, 2021 · 5 comments
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@Q-point
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Q-point commented Oct 11, 2021

Makefile:48: recipe for target 'aie' failed
make[1]: [aie] Error 255 (ignored)
if [ -f ../Module2.build.log ]; then cp ../Module2.build.log ./build.log 2>/dev/null; echo; echo "INFO: Look at the log file Debug/build.log for more details."; else echo "Warning: Build log file ../Module2.build.log doesn't exist."; fi; \

Warning: Build log file ../Module2.build.log doesn't exist.
if [ -d data ]; then echo "data exists"; else ln -s ../data data; fi;
aiesimulator --pkg-dir=Work --dump-vcd=foo
AIEsim feature license is found.
INFO: Executing config: Work/config/scsim_config.json
terminate called after throwing an instance of 'std::runtime_error'
what(): AIE Simulator config Json file missing, file: Work/config/scsim_config.json
/tools/Xilinx/Vitis/2021.1/aietools/bin/loader: line 312: 79090 Aborted (core dumped) "$RDI_PROG" "$@"
Makefile:52: recipe for target 'aiesim' failed
make[1]: *** [aiesim] Error 134
make[1]: Leaving directory '/home/dhq/Documents/Vitis-Tutorials/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/MatMult/Emulation-AIE'
Makefile:19: recipe for target 'all' failed
make: *** [all] Error 2

@Premduth
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@smitha-xilinx can you have someone take a look at this?

@OTremois
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The error on customer side seems to be in the aie compilation.
I tried on my side and compilation/simulation and visualization went fine.

Can we have more details on the AIE compilation error?

@Q-point
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Q-point commented Oct 12, 2021

The full log is below. It looks like the AIE is missing the config JSON file.
The error is due to missing files based on the logs.

Specifically:

" AIE Simulator config Json file missing, file: Work/config/scsim_config.json"

The environment is as below:

Vivado 2021.1

export SYSROOT=/home/dhq/Documents/Versal/xilinx-versal-common-v2021.1/ir/sysroots/cort$
export PLATFORM_REPO_PATHS=/home/dhq/Documents/Versal/xilinx_vck190_base_202110_1
export PERL=/usr/bin/perl
export EDGE_COMMON_SW=/home/dhq/Documents/Versal/xilinx-versal-common-v2021.1

Apart from that, I just issue make all under this directory.

dhq@dimo:~/Documents/Vitis-Tutorials/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/MatMult$ make all
make -C Emulation-AIE all
make[1]: Entering directory '/home/dhq/Documents/Vitis-Tutorials/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/MatMult/Emulation-AIE'
rm -rf ./Work ./data ./.tracecompass/.tracing ./Traces ./aiesim* ./ess* ./profile* ./xnwOut ./.Xil
find ./ -type f | grep -v Makefile | xargs rm -Rf
aiecompiler -v -dataflow -include="/include" -include="/../include" -include="../" -include="../aie" -include="../aie/aie_kernels" -include="../data" -target=hw   -platform=/home/dhq/Documents/Versal/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1.xpfm -workdir=./Work --xlopt=0 ../aie/graph.cpp
aietools : /tools/Xilinx/Vitis/2021.1/aietools
Version: Vitis AI Engine Compiler Release 2021.1
Build Info: SW Build 3286242 on Wed Jul 28 13:09:46 MDT 2021
Copyright(c) 2016-2020 Xilinx Inc.

INFO: [aiecompiler 77-297] Cmd Line : /tools/Xilinx/Vitis/2021.1/aietools/bin/unwrapped/lnx64.o/aiecompiler -v -dataflow -include=/include -include=/../include -include=../ -include=../aie -include=../aie/aie_kernels -include=../data -target=hw -platform=/home/dhq/Documents/Versal/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1.xpfm -workdir=./Work --xlopt=0 ../aie/graph.cpp 
Running Dispatch Server on port: 40947
INFO: [aiecompiler 77-349] Starting Dataflow Frontend with input '../aie/graph.cpp'
INFO: [aiecompiler 77-404] Executing Cmd: ${XILINX_VITIS_AIETOOLS}/tps/lnx64/gcc/bin/g++ -E -std=c++14 -D__ADF_FRONTEND__ -I/tools/Xilinx/Vitis/2021.1/aietools/include  -I .  -I /include -I /../include -I ../ -I ../aie -I ../aie/aie_kernels -I ../data -I ${XILINX_HLS}/include ../aie/graph.cpp > ./Work/temp/graph.ii
INFO: [aiecompiler 77-404] Executing Cmd: graph_preprocessor ./Work/temp/graph.ii -o ./Work/temp/graph.processed.ii -report-core-dump  -- -std=c++14  -ftemplate-depth=2048  -Wno-return-stack-address  -Wno-missing-declarations  -Wno-parentheses-equality  -Wno-shift-negative-value  
INFO: [aiecompiler 77-404] Executing Cmd: ${XILINX_VITIS_AIETOOLS}/tps/lnx64/gcc/bin/g++  -std=c++14  -I .  ./Work/temp/graph.processed.ii -o ./Work/temp/graph.out -L /tools/Xilinx/Vitis/2021.1/aietools/lib/lnx64.o -g -O0 -Wl,--unresolved-symbols=ignore-all  -Wno-return-stack-address  -Wno-missing-declarations  -lmeir_frontend  -ladf_api_frontend 
INFO: [aiecompiler 77-404] Executing Cmd: ./Work/temp/graph.out -I /include -I /../include -I ../ -I ../aie -I ../aie/aie_kernels -I ../data -workdir=./Work -aiearch=aie -log-level=1 --pl-axi-lite=0
INFO: [aiecompiler 77-749] Reading logical device VC1902.json
INFO: [aiecompiler 77-404] Executing Cmd: aieir_be --time-passes=0  --disable-om-fifo-insertion=false  --trace-plio-width=64  --pl-freq=0  --use-real-noc=true  --show-loggers=false  --fast-nonlinearfloats=false  --broadcast-enable-core=false  --high-performance=false  --kernel-address-location=false  --target=hw --swfifo-threshold=40  --single-mm2s-channel=false  --workdir=./Work  --exit-after=complete  --event-trace-config=  --test-iterations=-1  --stacksize=1024  --platform=/home/dhq/Documents/Versal/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1.xpfm  --event-trace-custom-config=  --disable-dma-cmd-alignment=false  --enable-ecc-scrubbing=true  --resource-manager=true  --write-partitioned-file=true  --schemafile=AIEGraphSchema.json  --include="/include" --include="/../include" --include="../" --include="../aie" --include="../aie/aie_kernels" --include="../data" --verify-switchconfig=true  --device=  --disable-multirate-analysis=false  --fastmath=false  --event-trace-advanced-mapping=0  --compute-heapsize=false  --log-level=1  --enable-reconfig=false  --aiesim-xrt-api=false  --gen-graph-cleanup=false  --use-canonical-net-names=false  --event-trace-port=plio --use-phy-shim=true  --xlopt=0  --pc-src-mapping=false  --pre-compile-kernels=false  --trace-aiesim-option=0  --aiearch=aie  --mapped-soln-udm=  --optimize-pktids=false  --no-init=false  --num-trace-streams=16  --aie-heat-map=false  --phydevice=  --fast-floats=false  --exec-timed=0  --pl-auto-restart=false  --routed-soln-udm=  --large-kernel-program=false  --enable-profiling=false  --disable-transform-merge-broadcast=false  --verbose=true  --use-async-rtp-locks=true  --repo-path=  --genArchive=false  --pl-axi-lite=false  --event-trace-bounding-box=  --logcfg-file=  --enable-reconfig-dma-autostart=false  --heapsize=1024  --logical-arch=  --nodot-graph=false  --shim-constraints=  --disable-dma-autostart=false  --disable-transform-broadcast-split=true  -json ./Work/temp/graph.json -sdf-graph ../aie/graph.cpp
AIEBuild feature license is found.
ERROR: [aiecompiler 77-4170] Unable to find specified platform : /home/dhq/Documents/Versal/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1.xpfm
/tools/Xilinx/Vitis/2021.1/aietools/bin/aieir_be: line 97: kill: (-18224) - No such process
ERROR: [aiecompiler 77-753] This application has discovered an exceptional condition from which it cannot recover while executing the following command
  >> aieir_be --time-passes=0  --disable-om-fifo-insertion=false  --trace-plio-width=64  --pl-freq=0  --use-real-noc=true  --show-loggers=false  --fast-nonlinearfloats=false  --broadcast-enable-core=false  --high-performance=false  --kernel-address-location=false  --target=hw --swfifo-threshold=40  --single-mm2s-channel=false  --workdir=./Work  --exit-after=complete  --event-trace-config=  --test-iterations=-1  --stacksize=1024  --platform=/home/dhq/Documents/Versal/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1.xpfm  --event-trace-custom-config=  --disable-dma-cmd-alignment=false  --enable-ecc-scrubbing=true  --resource-manager=true  --write-partitioned-file=true  --schemafile=AIEGraphSchema.json  --include="/include" --include="/../include" --include="../" --include="../aie" --include="../aie/aie_kernels" --include="../data" --verify-switchconfig=true  --device=  --disable-multirate-analysis=false  --fastmath=false  --event-trace-advanced-mapping=0  --compute-heapsize=false  --log-level=1  --enable-reconfig=false  --aiesim-xrt-api=false  --gen-graph-cleanup=false  --use-canonical-net-names=false  --event-trace-port=plio --use-phy-shim=true  --xlopt=0  --pc-src-mapping=false  --pre-compile-kernels=false  --trace-aiesim-option=0  --aiearch=aie  --mapped-soln-udm=  --optimize-pktids=false  --no-init=false  --num-trace-streams=16  --aie-heat-map=false  --phydevice=  --fast-floats=false  --exec-timed=0  --pl-auto-restart=false  --routed-soln-udm=  --large-kernel-program=false  --enable-profiling=false  --disable-transform-merge-broadcast=false  --verbose=true  --use-async-rtp-locks=true  --repo-path=  --genArchive=false  --pl-axi-lite=false  --event-trace-bounding-box=  --logcfg-file=  --enable-reconfig-dma-autostart=false  --heapsize=1024  --logical-arch=  --nodot-graph=false  --shim-constraints=  --disable-dma-autostart=false  --disable-transform-broadcast-split=true  -json ./Work/temp/graph.json -sdf-graph ../aie/graph.cpp.
Please check the output log for errors and fix those before you run the application.
/tools/Xilinx/Vitis/2021.1/aietools/bin/aiecompiler: line 82: kill: (-18099) - No such process
Makefile:48: recipe for target 'aie' failed
make[1]: [aie] Error 255 (ignored)
if [ -f ../Module2.build.log ]; then cp ../Module2.build.log ./build.log 2>/dev/null; echo; echo "INFO: Look at the log file Debug/build.log for more details."; else echo "Warning: Build log file ../Module2.build.log doesn't exist."; fi; \

Warning: Build log file ../Module2.build.log doesn't exist.
if [ -d data ]; then echo "data exists"; else ln -s ../data data; fi;
aiesimulator --pkg-dir=Work --dump-vcd=foo
AIEsim feature license is found.
INFO: Executing config: Work/config/scsim_config.json
terminate called after throwing an instance of 'std::runtime_error'
  what():  AIE Simulator config Json file missing, file: Work/config/scsim_config.json
/tools/Xilinx/Vitis/2021.1/aietools/bin/loader: line 312: 18322 Aborted                 (core dumped) "$RDI_PROG" "$@"
Makefile:52: recipe for target 'aiesim' failed
make[1]: *** [aiesim] Error 134
make[1]: Leaving directory '/home/dhq/Documents/Vitis-Tutorials/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/MatMult/Emulation-AIE'
Makefile:19: recipe for target 'all' failed
make: *** [all] Error 2

@OTremois
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Hi,

We can see at the end of the compilation the error:
ERROR: [aiecompiler 77-4170] Unable to find specified platform : /home/dhq/Documents/Versal/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1/xilinx_vck190_base_202110_1.xpfm

The problem comes from the way you defined the PLATFORM_REPO_PATH variable. It should be:
export PLATFORM_REPO_PATHS=/home/dhq/Documents/Versal

This modification should solve the compilation stage, and the simulation should be able to run.

@Q-point
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Q-point commented Oct 12, 2021

Hi,

I can confirm that works. Thank you , closing this.

@Q-point Q-point closed this as completed Oct 12, 2021
imrickysu pushed a commit that referenced this issue Dec 3, 2021
Add an optional description.json file.
vmayoral pushed a commit to vmayoral/Vitis-Tutorials that referenced this issue Jan 20, 2022
Updated Makefiles for changes to regressions
imrickysu pushed a commit that referenced this issue Nov 3, 2022
Add an optional description.json file.
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
db743e9 updat url in README.md and doc (Xilinx#113)
5d6466a Revert "nistp256 draft (Xilinx#107)" (Xilinx#112)
1d98667 nistp256 draft (Xilinx#107)
dec7844 Merge pull request Xilinx#109 from changg/test_timelimit
96f8c42 add memlimit

Co-authored-by: sdausr <[email protected]>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
f7d1abc Merge pull request Xilinx#122 from tuol/disable_2_case
ae62691 disable 2 case due to U250 platform change
3af143e Merge pull request Xilinx#118 from tuol/fix_cr_1122542
3e7f919 temporally disable L3/tests/mlp, due to U250 platform change
1728d13 update opts.cfg
98d3f3f Merge pull request Xilinx#117 from yuanqian/next
8639708 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831
18a7458 Merge pull request Xilinx#116 from changg/wa_u280_201920
86e28ef WA for xilinx_u280_xdma_201920_3
07abe54 Merge pull request Xilinx#114 from liyuanz/replace_cflags
7cb157c replace cflags with clflags
0196ded Merge pull request Xilinx#113 from changg/cov_fix
fc100b4 cov fix
b201f43 cov fix
14067e6 Merge pull request Xilinx#110 from liyuanz/next
bbe42e9 fix bug
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79db50c fix makefiles
984a71c update Makefile and utils
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28fe2ed replace whiltelist/blacklist to allowlist/blocklist
981b5a2 Merge pull request Xilinx#105 from changg/pr_104
2f45a63 add time for hw_build
a21b8db add time
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acce305 fix utils.mk
74536af fix utils.mk
3c0647e Merge pull request Xilinx#101 from liyuanz/next
fc26744 increase mem
7a1b220 Merge pull request Xilinx#99 from changg/fix_mks
055c521 fix typ
44ff7b9 fix utils.mk
4050d17 Merge pull request Xilinx#98 from liyuanz/replace_targets
b0157d6 update targes
e41fc60 Merge pull request Xilinx#96 from changg/metadata
f6d1e26 draft metadata
0bbb982 change 2021.2_stable_latest to 2022.1_stable_latest

Co-authored-by: sdausr <[email protected]>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
1b75f16 Merge pull request Xilinx#117 from liyuanz/add_m
cfc460f update
1b1fd0c Merge pull request Xilinx#116 from tuol/cr_1138695
990951d remove connectivity from opts.cfg
fcff114 Merge pull request Xilinx#112 from liyuanz/next
3c583c5 Merge branch 'next' into next
d148b7e Merge pull request Xilinx#115 from tuol/1135042_2
517ab80 fix description.json
875ee0b Merge pull request Xilinx#114 from tuol/cr_1135042_1
66a513b fix description.json
818c768 Merge pull request Xilinx#113 from tuol/cr_1138695
0dd07e2 add missing app.bin
246611d update mk
be55cf9 Merge pull request Xilinx#111 from tuol/cr_1138321_1
0a3d580 fix --nk option in connectivity setup
c48114c Merge pull request Xilinx#110 from tuol/cr_1138321
35c48bc fix makefile, description.json and connectivity setup of cscmv and cscmvSingleHBM
651be1e Merge pull request Xilinx#109 from tuol/cr_1135042
e4becb4 remove un-allowed properties from description.json
370087d Merge pull request Xilinx#107 from yuanqian/update_doc_next_portal
b4d95f0 Merge pull request Xilinx#108 from liyuanz/add_mem
5fb26ce add mem
90fb7b8 update
24b1d5e add memory
f454c44 update doc in next branch for portal
0ea11e4 Merge pull request Xilinx#105 from yuanqian/update_hls_pragma
3491287 Merge pull request Xilinx#106 from liyuanz/next
4c5d9a3 update
f81ca5a update hls pragma
ab89f67 change 2022.1_stable_latest to 2022.2_stable_latest
20d34e9 Merge pull request Xilinx#103 from tuol/fix_conf_py
5b45226 update conf.py
eb29003 Update Jenkinsfile

Co-authored-by: sdausr <[email protected]>
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