Vitis Platform Creation Tutorial for ZCU104: Emulation Does Not Work in u-boot #99
Assignees
Labels
PFM
Platform related issues
Comments
|
@imrickysu can you take a look? |
|
@Hamptonjc This error behavior looks very like the u-boot can't find boot.scr. |
imrickysu
changed the title
|
@imrickysu I can confirm boot.scr is in the image directory:
|
|
The full read out from the emulation console: |
imrickysu
pushed a commit
that referenced
this issue
Nov 20, 2021
vmayoral
pushed a commit
to vmayoral/Vitis-Tutorials
that referenced
this issue
Jan 20, 2022
Update AIE feature tutorials 02,03,04 for 2021.1_next
|
Hi @sven2314 Please check this issue and provide suggestions. |
|
Hi, @Hamptonjc |
imrickysu
pushed a commit
that referenced
this issue
Nov 3, 2022
CRTejaswi
pushed a commit
to CRTejaswi/amd-vitis
that referenced
this issue
Oct 3, 2023
37cba5b Clean WebpEnc 05b7e30 fixed index.html d3e13e2 modified 2021.1 to 2021.2 5d21faf Merge pull request Xilinx#107 from yunleiz/fnext 2f4abaa [gui] add description 0183ab5 Merge pull request Xilinx#106 from yunleiz/fnext 672b1db [clean]fixed CR https://jira.xilinx.com/browse/CR-1109840 010b477 fixed CR https://jira.xilinx.com/browse/CR-1109840 a64fbce Merge pull request Xilinx#103 from yuxiangz/move 480ec86 rm L2include 8d4685b Merge pull request Xilinx#102 from siyangw/next 383fda2 fix some problem for https://jira.xilinx.com/browse/CR-1107161 de542c3 Merge pull request Xilinx#101 from yuxiangz/rmwebp 0b648f2 rm webp 5ff5869 Merge pull request Xilinx#100 from liyuanz/next 4fa8680 replace XILINX_VIVADO with XILINX_HLS ffcb650 Merge pull request Xilinx#98 from yuxiangz/image_error e95ae01 fixed image error 891a16e Merge pull request Xilinx#97 from yuxiangz/readme b0c676e fixed benchmark c04bc74 update release 1b28512 fixed kernel doc c853e54 update benchmark wepb 573f3db revise code struct 451450e add wepb api 7d4d309 Merge pull request Xilinx#95 from yuxiangz/readme b2e9ddd fixed error for readme 9f32eb2 Merge pull request Xilinx#94 from yuxiangz/readme 8974955 fixed error for readme ca242c9 Merge pull request Xilinx#91 from yunleiz/fnext 53b7203 [doc] fixed pik profm in next b53c54c [doc] fixed pik profm in net 4152274 Merge pull request Xilinx#90 from yunleiz/fnext f4a9082 [doc] fixed readme on next a1b4baa Merge pull request Xilinx#88 from siyangw/fix_sw_emu 4bbba7f change 2021.1_stable_latest to 2021.2_stable_latest REVERT: 48cc941 Merge pull request Xilinx#99 from yuxiangz/cr-640 REVERT: c373206 fixed image error for master REVERT: 4d5db06 Merge pull request Xilinx#92 from yunleiz/fmaster REVERT: 19e4a69 [doc] fixed pik profm in master REVERT: 74e5c6a Merge pull request Xilinx#89 from yunleiz/fmaster REVERT: 2f9cc50 [doc] fixed readme on master REVERT: 587473b Merge pull request Xilinx#87 from siyangw/fix_sw_emu REVERT: 41a249c create master branch from next branch git-subtree-dir: codec git-subtree-split: 37cba5bec8072c63d0d75433cebe2467cd74f401 Co-authored-by: sdausr <[email protected]>
CRTejaswi
pushed a commit
to CRTejaswi/amd-vitis
that referenced
this issue
Oct 3, 2023
f7d1abc Merge pull request Xilinx#122 from tuol/disable_2_case ae62691 disable 2 case due to U250 platform change 3af143e Merge pull request Xilinx#118 from tuol/fix_cr_1122542 3e7f919 temporally disable L3/tests/mlp, due to U250 platform change 1728d13 update opts.cfg 98d3f3f Merge pull request Xilinx#117 from yuanqian/next 8639708 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 18a7458 Merge pull request Xilinx#116 from changg/wa_u280_201920 86e28ef WA for xilinx_u280_xdma_201920_3 07abe54 Merge pull request Xilinx#114 from liyuanz/replace_cflags 7cb157c replace cflags with clflags 0196ded Merge pull request Xilinx#113 from changg/cov_fix fc100b4 cov fix b201f43 cov fix 14067e6 Merge pull request Xilinx#110 from liyuanz/next bbe42e9 fix bug 257677d Merge pull request Xilinx#109 from changg/pr_108 79db50c fix makefiles 984a71c update Makefile and utils daf9820 Merge pull request Xilinx#106 from liyuanz/replace_blacklist 28fe2ed replace whiltelist/blacklist to allowlist/blocklist 981b5a2 Merge pull request Xilinx#105 from changg/pr_104 2f45a63 add time for hw_build a21b8db add time 7256e35 add time 5f2c36a Merge pull request Xilinx#102 from changg/add_extraflags acce305 fix utils.mk 74536af fix utils.mk 3c0647e Merge pull request Xilinx#101 from liyuanz/next fc26744 increase mem 7a1b220 Merge pull request Xilinx#99 from changg/fix_mks 055c521 fix typ 44ff7b9 fix utils.mk 4050d17 Merge pull request Xilinx#98 from liyuanz/replace_targets b0157d6 update targes e41fc60 Merge pull request Xilinx#96 from changg/metadata f6d1e26 draft metadata 0bbb982 change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <[email protected]>
CRTejaswi
pushed a commit
to CRTejaswi/amd-vitis
that referenced
this issue
Oct 3, 2023
00c1121 Merge pull request Xilinx#101 from changg/wa_u280 6353429 fix 15dddbb Merge pull request Xilinx#100 from changg/wa_u280 bb26130 wa for u280 f33813e Merge pull request Xilinx#99 from changg/fix_meta 78bfba6 fix meta Co-authored-by: sdausr <[email protected]>
|
Closing the thread as there are no open concerns. Thanks |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Following: https://github.com/Xilinx/Vitis-Tutorials/tree/2020.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104#step-by-step-tutorial
During step 4, test 2 "Run Vector Addition Application", when running HW-emulation I get the following in the emulation console of the Vitis IDE:
Note: I am using branch 2020.2, matching my Xilinx tool versions.
Any ideas?
The text was updated successfully, but these errors were encountered: