follow up the tutorial but error happen #90
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OK I find there are some extra steps that are need, in the application note just alongside the repo.. you really should update the documentation.. |
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TechPubs Edits for Versal System Design Clocking Tutorial
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37cba5b Clean WebpEnc 05b7e30 fixed index.html d3e13e2 modified 2021.1 to 2021.2 5d21faf Merge pull request Xilinx#107 from yunleiz/fnext 2f4abaa [gui] add description 0183ab5 Merge pull request Xilinx#106 from yunleiz/fnext 672b1db [clean]fixed CR https://jira.xilinx.com/browse/CR-1109840 010b477 fixed CR https://jira.xilinx.com/browse/CR-1109840 a64fbce Merge pull request Xilinx#103 from yuxiangz/move 480ec86 rm L2include 8d4685b Merge pull request Xilinx#102 from siyangw/next 383fda2 fix some problem for https://jira.xilinx.com/browse/CR-1107161 de542c3 Merge pull request Xilinx#101 from yuxiangz/rmwebp 0b648f2 rm webp 5ff5869 Merge pull request Xilinx#100 from liyuanz/next 4fa8680 replace XILINX_VIVADO with XILINX_HLS ffcb650 Merge pull request Xilinx#98 from yuxiangz/image_error e95ae01 fixed image error 891a16e Merge pull request Xilinx#97 from yuxiangz/readme b0c676e fixed benchmark c04bc74 update release 1b28512 fixed kernel doc c853e54 update benchmark wepb 573f3db revise code struct 451450e add wepb api 7d4d309 Merge pull request Xilinx#95 from yuxiangz/readme b2e9ddd fixed error for readme 9f32eb2 Merge pull request Xilinx#94 from yuxiangz/readme 8974955 fixed error for readme ca242c9 Merge pull request Xilinx#91 from yunleiz/fnext 53b7203 [doc] fixed pik profm in next b53c54c [doc] fixed pik profm in net 4152274 Merge pull request Xilinx#90 from yunleiz/fnext f4a9082 [doc] fixed readme on next a1b4baa Merge pull request Xilinx#88 from siyangw/fix_sw_emu 4bbba7f change 2021.1_stable_latest to 2021.2_stable_latest REVERT: 48cc941 Merge pull request Xilinx#99 from yuxiangz/cr-640 REVERT: c373206 fixed image error for master REVERT: 4d5db06 Merge pull request Xilinx#92 from yunleiz/fmaster REVERT: 19e4a69 [doc] fixed pik profm in master REVERT: 74e5c6a Merge pull request Xilinx#89 from yunleiz/fmaster REVERT: 2f9cc50 [doc] fixed readme on master REVERT: 587473b Merge pull request Xilinx#87 from siyangw/fix_sw_emu REVERT: 41a249c create master branch from next branch git-subtree-dir: codec git-subtree-split: 37cba5bec8072c63d0d75433cebe2467cd74f401 Co-authored-by: sdausr <[email protected]>
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47283e6 add description in description.json (Xilinx#103) 4b98198 add crc32c (Xilinx#88) f89c4fd change doc format, and include guard name (Xilinx#102) a7a98cc optimize adler32's timing (Xilinx#90) Co-authored-by: sdausr <[email protected]>
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bf99958 update conf.py for release version and add release note (Xilinx#105) 47283e6 add description in description.json (Xilinx#103) 4b98198 add crc32c (Xilinx#88) f89c4fd change doc format, and include guard name (Xilinx#102) a7a98cc optimize adler32's timing (Xilinx#90) Co-authored-by: sdausr <[email protected]>
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695eee4 update version 04f4d5f fix typos 64588a9 update version b763a17 update RTM 3D forward test 1773e6e Merge pull request Xilinx#90 from changg/fix_time eee98af fix time 4953200 Merge pull request Xilinx#89 from yuanqian/next dd4a215 increase max time 8b66520 Merge pull request Xilinx#88 from yuanqian/next b1c2661 increase memory due to memory limit in daily regression 2b1e855 Merge pull request Xilinx#87 from yuanqian/next e8cc376 increase max memory in runtime ee272e1 increase maxruntime 134abba Merge pull request Xilinx#86 from liyuanz/next 3aa7fd8 fix bug about LD_LIBRARY_PATH in utils.mk 5f047f8 Merge pull request Xilinx#85 from liyuanz/next 956cd0b fix CR about Linking XRT native API on CentOS 8 fails Co-authored-by: sdausr <[email protected]> have 100% pass rate in daily regression
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b8aa0ac Merge pull request Xilinx#98 from changg/round2-mk 0dafa9e fix 69ce1de Merge pull request Xilinx#97 from changg/round2-mk 33635fb fix utils.mk bb09f85 Merge pull request Xilinx#96 from tuol/fix_cr_1125397 26bfd12 upate description.json for GUI 6142bf4 Merge pull request Xilinx#95 from tuol/fix_cr1110852 18b6b69 add description for cscmvSingleHBM 489d6fe Merge pull request Xilinx#94 from changg/wa_u280 c83ed11 WA for u280 70d666c Revert "wa for xilinx_u280_xdma_201920_3" 27306c5 Merge pull request Xilinx#93 from changg/wa_u280_2019 2b4ec88 wa for xilinx_u280_xdma_201920_3 af1d094 Merge pull request Xilinx#92 from liyuanz/replace_cflags a9ff957 replace cflags with clflags eb58a83 Merge pull request Xilinx#91 from tuol/fix_cr_1110852 c9ca9ab add description to L2/tests/cscmvSingleHbm b8e0210 Merge pull request Xilinx#90 from tuol/fix_cr_1083211 75204c8 remove 'exclude' from description.json 965b2e0 Merge pull request Xilinx#88 from liyuanz/replace_blacklist 0e87eee replace whiltelist/blacklist to allowlist/blocklist ad26de7 Merge pull request Xilinx#87 from liyuanz/next 3db258c increase time def14fe Merge pull request Xilinx#85 from changg/add_extraflags f8a6122 fix makefile 031de2c Merge pull request Xilinx#84 from liyuanz/next f10953c increase time 4745f24 Merge pull request Xilinx#83 from changg/fix_utils 6fb2652 fix utisl 7d9278f Merge pull request Xilinx#82 from liyuanz/replace_targets c1c2de5 update targes 68ae52e Merge pull request Xilinx#80 from changg/metadata 6225d51 draft metadata files e74cf2b change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <[email protected]>
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b0ee140 Merge pull request Xilinx#92 from liyuanz/add_mmm db0107b update 1a68c39 Merge pull request Xilinx#91 from liyuanz/add_mm 533e836 update ab8f933 Merge pull request Xilinx#90 from tianminr/readme_modification b99355a update readme ba67162 Merge pull request Xilinx#89 from tianminr/doc 0c1f13d update api.json 8845ce5 Merge pull request Xilinx#88 from tianminr/doc 25561cf refine docs 5d55ecf Merge pull request Xilinx#87 from tianminr/plane_wave_refine 74da1b7 fixed for json file and coding-style daff5ca Merge remote-tracking branch 'xf_ultrasound/next' into plane_wave_refine 0714894 Merge pull request Xilinx#86 from tianminr/code_clean ba7d629 refine planewave regression c353e1c clean for old window apis 23ede93 Merge pull request Xilinx#85 from tianminr/regression_refine 9af26a9 modificaiton for docson 23.1 8d81605 scanline timing update d98d78e regression refine e75b377 Merge pull request Xilinx#84 from tianminr/next_clean b5fa450 clean kernels.hpp fdafd55 next branch clean Co-authored-by: sdausr <[email protected]>
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Hi I am following this tutorial https://github.com/Xilinx/Vitis-Tutorials/blob/c6226467aff75d9647c45ef82e918e585496b76c/Hardware_Accelerators/Feature_Tutorials/01-rtl_kernel_workflow/package_ip.md
All steps are OK but at the final step to package the xo file: I get several errors report:
ERROR: [Common 17-170] Unknown option '-ctrl_protocol', please type 'package_xo -help' for usage info. package_xo -force -xo_path /home/xeniro/vivado_prj/rtl_kernel/rtl_kernel.srcs/sources_1/imports/xo/VDD_AB.xo -kernel_name Vadd_AB -ip_directory /home/xeniro/vivado_prj/rtl_kernel/rtl_kernel.srcs/sources_1/imports/IP WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found. ERROR: [IP_Flow 19-5629] Bus Interface 'ap_clk': FREQ_HZ bus parameter is missing from clock interface. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. ERROR: [IP_Flow 19-5630] The XPM_LIBRARIES property values should be 'XPM_MEMORY', 'XPM_FIFO' and 'XPM_CDC' for this IP. ERROR: [Ipptcl 7-1485] check_integrity: Integrity check failed. ERROR: [Common 17-39] 'ipx::check_integrity' failed due to earlier errors. ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'ipx::check_integrity' failed due to earlier errors.Note I am using Vitis/Vavado 2020.1
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