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Yolov4 using VOC Data Set and converting to Caffe Tutorial #80

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Liu-guoxin opened this issue Jun 1, 2021 · 1 comment
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Yolov4 using VOC Data Set and converting to Caffe Tutorial #80

Liu-guoxin opened this issue Jun 1, 2021 · 1 comment

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@Liu-guoxin
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set number of classes to 20 for each output layer
set filter size of convolutional layer before each output layers to 75

how to set classes and filter.

I cant run bash scripts/run_vai_c_zu104.sh success .
alvincla pushed a commit that referenced this issue Jun 23, 2021
Merge pull request #80 from randyh/master
007df73 
added note regarding scp of files from QEMU
@Premduth
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Please try this in

https://github.com/Xilinx/Vitis-AI-Tutorials

All ML tutorials moved there

imrickysu pushed a commit that referenced this issue Aug 20, 2021
Merge pull request #80 from randyh/master
6cc90c9 
added note regarding scp of files from QEMU
imrickysu pushed a commit that referenced this issue Nov 7, 2021
Update AI Feature 12 script to install python packages for regression (…
8c87333 
…#80)
imrickysu pushed a commit that referenced this issue Nov 3, 2022
Update AI Feature 12 script to install python packages for regression (…
fd4a476 
…#80)
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
Squashed 'sparse' changes from a0f15de..b8aa0ac (#545)
61a64e9 
b8aa0ac Merge pull request Xilinx#98 from changg/round2-mk
0dafa9e fix
69ce1de Merge pull request Xilinx#97 from changg/round2-mk
33635fb fix utils.mk
bb09f85 Merge pull request Xilinx#96 from tuol/fix_cr_1125397
26bfd12 upate description.json for GUI
6142bf4 Merge pull request Xilinx#95 from tuol/fix_cr1110852
18b6b69 add description for cscmvSingleHBM
489d6fe Merge pull request Xilinx#94 from changg/wa_u280
c83ed11 WA for u280
70d666c Revert "wa for xilinx_u280_xdma_201920_3"
27306c5 Merge pull request Xilinx#93 from changg/wa_u280_2019
2b4ec88 wa for xilinx_u280_xdma_201920_3
af1d094 Merge pull request Xilinx#92 from liyuanz/replace_cflags
a9ff957 replace cflags with clflags
eb58a83 Merge pull request Xilinx#91 from tuol/fix_cr_1110852
c9ca9ab add description to L2/tests/cscmvSingleHbm
b8e0210 Merge pull request Xilinx#90 from tuol/fix_cr_1083211
75204c8 remove 'exclude' from description.json
965b2e0 Merge pull request Xilinx#88 from liyuanz/replace_blacklist
0e87eee replace whiltelist/blacklist to allowlist/blocklist
ad26de7 Merge pull request Xilinx#87 from liyuanz/next
3db258c increase time
def14fe Merge pull request Xilinx#85 from changg/add_extraflags
f8a6122 fix makefile
031de2c Merge pull request Xilinx#84 from liyuanz/next
f10953c increase time
4745f24 Merge pull request Xilinx#83 from changg/fix_utils
6fb2652 fix utisl
7d9278f Merge pull request Xilinx#82 from liyuanz/replace_targets
c1c2de5 update targes
68ae52e Merge pull request Xilinx#80 from changg/metadata
6225d51 draft metadata files
e74cf2b change 2021.2_stable_latest to 2022.1_stable_latest

Co-authored-by: sdausr <[email protected]>
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@Premduth @Liu-guoxin