ERROR: [v++ 60-1576] Input Object file validation failed: zip_exception: Failed to open zip archive for reading #82
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SOLVED: I have been missing the Anyway, the error message was useless. |
imrickysu
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…ession testing (#82) * Adding description.json + Modifying ps_apps Makefiles to support regression testing * Update README.md: http links pointing to 2021.2 documentation
vmayoral
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update for AIE packet switch 2021.1
imrickysu
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…ession testing (#82) * Adding description.json + Modifying ps_apps Makefiles to support regression testing * Update README.md: http links pointing to 2021.2 documentation
CRTejaswi
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b8aa0ac Merge pull request Xilinx#98 from changg/round2-mk 0dafa9e fix 69ce1de Merge pull request Xilinx#97 from changg/round2-mk 33635fb fix utils.mk bb09f85 Merge pull request Xilinx#96 from tuol/fix_cr_1125397 26bfd12 upate description.json for GUI 6142bf4 Merge pull request Xilinx#95 from tuol/fix_cr1110852 18b6b69 add description for cscmvSingleHBM 489d6fe Merge pull request Xilinx#94 from changg/wa_u280 c83ed11 WA for u280 70d666c Revert "wa for xilinx_u280_xdma_201920_3" 27306c5 Merge pull request Xilinx#93 from changg/wa_u280_2019 2b4ec88 wa for xilinx_u280_xdma_201920_3 af1d094 Merge pull request Xilinx#92 from liyuanz/replace_cflags a9ff957 replace cflags with clflags eb58a83 Merge pull request Xilinx#91 from tuol/fix_cr_1110852 c9ca9ab add description to L2/tests/cscmvSingleHbm b8e0210 Merge pull request Xilinx#90 from tuol/fix_cr_1083211 75204c8 remove 'exclude' from description.json 965b2e0 Merge pull request Xilinx#88 from liyuanz/replace_blacklist 0e87eee replace whiltelist/blacklist to allowlist/blocklist ad26de7 Merge pull request Xilinx#87 from liyuanz/next 3db258c increase time def14fe Merge pull request Xilinx#85 from changg/add_extraflags f8a6122 fix makefile 031de2c Merge pull request Xilinx#84 from liyuanz/next f10953c increase time 4745f24 Merge pull request Xilinx#83 from changg/fix_utils 6fb2652 fix utisl 7d9278f Merge pull request Xilinx#82 from liyuanz/replace_targets c1c2de5 update targes 68ae52e Merge pull request Xilinx#80 from changg/metadata 6225d51 draft metadata files e74cf2b change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <[email protected]>
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f0e0005 Merge pull request Xilinx#83 from liyuanz/add_time 361913d add time 64ea0f9 Merge pull request Xilinx#82 from liyuanz/next 8386360 update 370bb26 Merge pull request Xilinx#81 from liyuanz/next 4716b14 add memory or time 2b41485 Merge pull request Xilinx#79 from yuxiangz/makefile a5df524 update makefile for hw_emu bc265f0 Merge pull request Xilinx#77 from tianminr/L3_dev bd9b7c5 Merge pull request Xilinx#76 from yuxiangz/sizein d2a2ab6 update scanline case 591cebc add golden out size 4898af0 push request for regress 4cee657 turn up c13c69b update error kernel for kernel_ratio setting 1379c0d Merge remote-tracking branch 'xf_ultrasound/next' into L3_dev 43ecd58 update L2 graph & kernel ratio setup for scanline 5c9a2e5 update host 8a8bc80 Merge pull request Xilinx#71 from yuxiangz/graph_l3 bd69baf turn memory up 3 b7ee6a5 Merge pull request Xilinx#73 from siyangw/IO_Dev f516f8e Merge pull request Xilinx#72 from tianminr/L3_dev a467fa5 turn memory up 9d3c0cc revise description.json bbaee77 Merge pull request Xilinx#70 from siyangw/IO_Dev f0d9dd8 scanline graph update 22db53e scanline sw_emu pass b0487bd update port name 4404027 sw_emu pass 2571dd9 plane wave pass sw_emu 19e4cc3 Merge remote-tracking branch 'ultrasound/next' into IO_Dev 081a881 plane wave pass x86sim and aiesim 5c27d04 build graph for L3 Co-authored-by: sdausr <[email protected]>
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I am trying to compile the vadd example provided with Vitis 2020.2. As I want to prepare my custom Makefile I have started with super simple stuff.
I first run
It seems to work correctly.
Then, I run
However, during the built I get following error:
I have tried to google the problem, but without success.
Theoretically I use OS which is supported by Xilinx, Ubuntu 20.04.
Does anyone know what might be wrong?
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