[SYCL][Doc] Get started guide clean-up #1697
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- Removed instructions to make a DPCPP_HOME/build directory - Fix issues reported by Markdown linter Signed-off-by: Alexey Bader <[email protected]>
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vladimirlaz
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pvchupin
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May 18, 2020
| ### Deployment | ||
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| TODO: add instructions how to deploy built DPC++ toolchain. | ||
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| ## Use DPC++ toolchain | ||
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| ### Using the DPC++ toolchain on CUDA platforms |
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Can you please move this section to the bottom of "Use DPC++ toolchain"?
Also please update Table of contents so that this section appears there.
| @@ -308,21 +316,25 @@ cmake -DIntel_SYCL_ROOT=%DPCPP_HOME%\deploy -DSYCL_IMPLEMENTATION=Intel_SYCL ... | |||
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Please update Table of Content with Build Doxygen documentation
| @@ -493,8 +508,8 @@ int main() { | |||
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Please update Table of Content with "Code the program for a specific GPU"
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My suggestions could be done as part of this cleanup or the next cleanup. |
pvchupin
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May 18, 2020
alexbatashev
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May 20, 2020
* sycl: (65 commits) [SYCL] Host task implementation (intel#1471) [SYCL] Update getting dependencies documentation (intel#1699) [SYCL] Fix types and transparent functors recognition in reduction (intel#1709) [SYCL][Doc] Get started guide clean-up (intel#1697) Add --spirv-fp-contract={on|off|fast} option (intel#509) [SYCL][Doc] Fix tbb target path in Get Started Guide. (intel#1695) [SYCL] Add support for kernel name types templated using enums. (intel#1675) [Driver][SYCL] Make -std=c++17 the default for DPC++ (intel#1662) AllocaInst should store Align instead of MaybeAlign. [X86] Replace selectScalarSSELoad ComplexPattern with PatFrags to handle the 3 types of loads we currently match. Harden IR and bitcode parsers against infinite size types. Revert "[nfc] test commit" [nfc] test commit Expose IRGen API to add the default IR attributes to a function definition. The release notes for ObjCBreakBeforeNestedBlockParam was placed between the release note for IndentCaseBlocks and its example code [VectorCombine] forward walk through instructions to improve chaining of transforms [PhaseOrdering] add vector reduction tests; NFC [InstCombine] Clean up alignment handling (NFC) [ARM] Patterns for VQSHRN [VectorCombine] add reduction-like patterns; NFC ...
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Nov 8, 2022
) Community restricted readnone, readonly and writeonly attributes to be only function parameter attributes. This patch aligns the translator with llvm.org. It also fixes a bug, when readnone attribute is being mapped to NoWrite SPIR-V function parameter attribute. Signed-off-by: Sidorov, Dmitry <[email protected]> Signed-off-by: Sidorov, Dmitry <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@c1fe5fe
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Signed-off-by: Alexey Bader [email protected]