March 2021 Bump #27
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March 2021 Bump #27
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We add newly defined hypervisor CSRs and allow M/HS-mode to access these CSRs. The MRET, SRET, ECALL and WFI instructions have also been updated so that virt-to-novirt switch and exception cause is based on HART virtualization state. Subsequent patches will implement two-stage page tables, HFENCE instructions and HSV/HLV instructions. Signed-off-by: Anup Patel <[email protected]>
We extend our existing MMU implementation to support two-stage translation when running VS-mode for RISC-V hypervisor extension. Signed-off-by: Anup Patel <[email protected]>
We add new HFENCE, HLV, and HSV instructions for HS-mode which are defined as part of the RISC-V hypervisor extension. Signed-off-by: Anup Patel <[email protected]>
We add bootargs command-line option to Spike which allows us to provide custom kernel parameters to Linux and Xvisor. Signed-off-by: Anup Patel <[email protected]>
It is very inconvenient to always embed kernel flat image into OpenSBI for booting Linux/Xvisor on Spike. We add optional "--kernel" command line option for spike. Using this new option, users can specify kernel flat image separately and OpenSBI ELF separately. Signed-off-by: Anup Patel <[email protected]>
RISC-V H-Extension v0.6.1 Support
Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Some UCB implementations once used this to represent a pipeline bubble. But this encoding is reserved for future standard HINT use. Resolves #503
Incorporate RVV 1.0 vtype layout change
Signed-off-by: Chih-Min Chao <[email protected]>
some dump and comparison tool may depennd the initial state of vector register. Signed-off-by: Chih-Min Chao <[email protected]>
The command parser still can accept SLEN but the value is not stored in implementation Signed-off-by: Chih-Min Chao <[email protected]>
The original name misses the 'i' in instruction mae vamoswape8 -> vamoswapei8 Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
They aren't arch state Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
except for load/store instructions
0 : all instruction can't have non-zero vstart
not 0 : all instruction can have non-zero vstart if it is not required
vstart must be zero in spec
the default value is 1
Signed-off-by: Chih-Min Chao <[email protected]>
The change comes from the generation order in riscv-opcodes. The original definition is placed in opcode-system but the new one is placed in separated opcode-rv64h and opcode-rv32h. Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
Rvv enhance vstart
Op hypvervisor
* make value display depend on max_xlen * try to make spike look for correct pk * PRIx64 instead of PRIx32, TARGET_ARCH back to 64 * 32 bit memory data, exception epc and tval
* Implement JTAG BYPASS register. This allows spike to put into a virtual scan chain with other remote_bitbang JTAG devices. * Initialize bypass to 0. Also change what we do on what edge. In theory that's more correct but in practice it doesn't make a difference.
At compile time, gcc complains with:
../riscv/processor.cc:787:94: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 5 has type ‘uint64_t {aka long unsigned int}’ [-Wformat=]
The variable 'bits' is an uint64_t, so that PRIx64 should be used to print it out.
* rvp: add 8/16 bits add/sub simd instructions * rvp: add 8/16 bits shift simd instructions * rvp: add 8/16 bits compare simd instructions * rvp: add 8/16 bits multiply simd instructions * rvp: add 8/16 bits misc simd instructions * rvp: add 8 bits unpacking simd instructions * rvp: update suppported extention and add restriction * rvp: update encoding.h and riscv.mk.in * rvp: disasm: add simd instruction support * rvp: update readme for p-ext simd instructions * rvp: fix rvp support version * rvp: update encoding.h generated from riscv-opcode p-ext branch * rvp: rename some macro argument * rvp: add pk[bb,bt,tt,tb][16,32] instructions * rvp: add kadd32, [su]maqa[_su] instructions * rvp: fix missing initial value of pd * rvp: add msw 32x32 multiply & add instructions * rvp: change to use extract64 * rvp: add msw 32x16 multiply & add instructions * rvp: fix some style * rvp: change reduction marcro definition * rvp: add signed 16x32 add/subtract instructions * rvp: use stdint to replace hardcode max/minimum * rvp: refactor some p-ext macro code * rvp: add partial simd miscellaneous instructions * rvp: add signed 16 x 64 add/subtract Instructions * rvp: add 64-bit add & sub instructions * rvp: add 32-bit mul with 64-bit add/sub instructions * rvp: add 16-bit mul with 64-bit add/sub instructions * rvp: disasm: add 64 bit profile instruction support * rvp: add Q15 saturation instructions * rvp: fix kmar64/kmsr64 saturation behavior * rvp: add 32-bit computation instructions * rvp: add rdov/clrov and fix khm16 behavior of setting OV flag * rvp: add non simd miscellaneous instructions * rvp: add Q31 saturation instructions * rvp: disasm: add non-simd instruction support * rvp: add 32 bits add/sub simd instructions * rvp: fix left shift saturation bug * rvp: add 32 bits shift simd instructions * rvp: add rv64 only Q15 simd instructions * rvp: add rv64 only 32-bit multiply instructions * rvp: add rv64 only 32-bit miscellaneous instructions * rvp: add rv64 only 32-bit mul & add instructions * rvp: add rv64 only 32-bit parallel mul & add instructions * rvp: add rv64 only non-simd 32-bit shift instructions * rvp: disasm: remove redundant tab * rvp: disasm: add rv64 only instructions support * rvp: change ov csr to ucode to match v0.5.2 spec * rvp: update readme for p-ext 0.5.2 * rvp: update to p-ext v0.9.1 * rvp: update to p-ext v0.9.2 * rvp: update readme for p-ext 0.9.2 * rvp: fix macro for PKxx16 & PKxx32 commands. * rvp: fix missing for in PKxxdd macro * Sign-extension for p-ext insns * * Fixed uclipNN insns while sh >> 64 is an UB. * Added missing OV * Added missing sext_xlen * Remove unused macroses * Sign extension for RD_PAIR macro * rvp: remove lost tab Co-authored-by: Mark Fedorov <[email protected]>
hgatp.PPN should be writable even if the new MODE is invalid. Additionally, mask off the two LSBs, as the spec allows.
For V=0 or V=1 writes to satp, the entire write is suppressed if the MODE is not supported. For V=0 writes to vsatp, only normal WARLness applies.
This is a bug in the spec that will be changed in the next few days.
Co-authored-by: zhongcy <[email protected]>
The B extension still implies the presence of Zba/Zbb/Zbc/Zbs.
With recent compilers on recent computers, the much simpler version of the code is actually slightly faster. I suspect, but haven't proven, that more accurate indirect jump prediction is the main explanation. Reduced I$ pressure might be a secondary factor.
After the privilege draft-20191120-569d071, the section 3.1.6.3 says "An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0. Signed-off-by: Chih-Min Chao <[email protected]>
problem:
when the following memory region is specified
-m0x00410000:0x1000,
0x00410200:0x1000,
0x00410400:0x1000,
0x00410600:0x1000,
0x00410800:0x1000,
0x00411000:0x1000,
0x00412000:0x1000,
0x00413000:0x1000,
0x00414000:0x1000
The error is
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR: Input tree has errors, aborting (use -f to force output)
cause:
the merge_overlapping_memory_regions works not well in partial overlap case
change:
1. use forward way to avoid weird reverse iterator behavior in C++
2. use address but not page number since the base addresses are
all aligned in make_mems
Signed-off-by: Chih-Min Chao <[email protected]>
allow --isa=rv32gc_xdummy_xabcd_xdef Signed-off-by: Chih-Min Chao <[email protected]>
Signed-off-by: Chih-Min Chao <[email protected]>
They have been remove in 0.10 spec Signed-off-by: Chih-Min Chao <[email protected]>
Misc fix 2021 04 21
- Reverts the AES32 and SM4 instruction encodings back to a normal R-type encoding, per the advice of the architecture reviewers. On branch scalar-crypto-v0.9.2 Changes to be committed: modified: riscv/encoding.h modified: riscv/insns/aes32dsi.h modified: riscv/insns/aes32dsmi.h modified: riscv/insns/aes32esi.h modified: riscv/insns/aes32esmi.h modified: riscv/insns/sm4ed.h modified: riscv/insns/sm4ks.h
scalar-crypto: Encoding fixes for v0.9.2
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Reopening #24 for a branch in this repo. Part of ucb-bar/chipyard#837.