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March 2021 Bump #27

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Jun 9, 2021
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9af85e3
Implement hypervisor CSRs read/write
avpatel Jun 13, 2020
b75aff9
Implement hypervisor two-stage MMU
avpatel Jun 21, 2020
564ed97
Implement new instructions of hypervisor extension
avpatel Jun 19, 2020
2cb19ac
Add bootargs command-line option to Spike
avpatel Jun 22, 2020
dff90a8
Add kernel command line option for spike
avpatel Jun 22, 2020
ecc039e
Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1
aswaterman Jul 9, 2020
f4904b6
rvv: fix viota.m dst and src overlapping rule (#504)
chihminchao Jul 13, 2020
759f4eb
commitlog: fix vmvnfr.v register information (#506)
chihminchao Jul 15, 2020
8d860c1
Fix legalize_privilege for extension H (#508)
abhinay-kayastha Jul 17, 2020
67b7edd
Remove deprecated decoding of xor x0,x0,x0
aswaterman Jul 22, 2020
308b6db
Incorporate RVV 1.0 vtype layout change
aswaterman Jul 28, 2020
6275cdf
Merge pull request #517 from riscv/rvv-1.0-vtype
aswaterman Jul 29, 2020
3784c3f
rvv: disasm: fix missing vamoorei operands
chihminchao Jul 23, 2020
fabc3c4
rvv: initialize vector register as zero
chihminchao Jul 23, 2020
f2d6531
rvv: remove slen
chihminchao Jul 15, 2020
4d6086e
rvv: op: fix amo naming
chihminchao Jul 15, 2020
3075210
rvv: op: rearrange some instruction since generation order change
chihminchao Jul 15, 2020
effb92a
rvv: add new whole reg load/store instructions
chihminchao Jul 15, 2020
cdda51c
rvv: add vrgatherei16.vv
chihminchao Jul 23, 2020
a602aa5
rvv: remove veew/vemul state
chihminchao Jul 30, 2020
a448260
rvv: remove isa string zvamoand zvlsseg
chihminchao Jul 30, 2020
9fadb08
rvv: fix frac_lmul get function
chihminchao Jul 30, 2020
5a107c6
f16: fix Nan-Box macro
chihminchao Jul 21, 2020
6859ccf
Merge pull request #519 from chihminchao/rvv-pre-1.0
aswaterman Jul 30, 2020
959700e
op: rvv: fix pesudo code instructions
chihminchao Aug 3, 2020
6e4977a
rvv: add 'vstartalu" option to --varch arugment
chihminchao Aug 3, 2020
f5e4f0c
op: rearrange hypbervisor op/csr/cause
chihminchao Jul 15, 2020
7775c6f
op: hyperviosr: fix exception code and name
chihminchao Aug 3, 2020
99eab5e
Merge pull request #520 from chihminchao/rvv-enhance-vstart
aswaterman Aug 4, 2020
da34b0e
Merge pull request #521 from chihminchao/op-hypvervisor
aswaterman Aug 4, 2020
5e073ef
Add option to dissable implicit ebreak in program buffer
sobuch Aug 11, 2020
0ebb8a9
Merge pull request #527 from sobuch/optional-impebreak
aswaterman Aug 11, 2020
6160ee9
mcounteren does not exist if U-mode is not implemented
aswaterman Aug 12, 2020
30a7419
rvv: fix vrgatherei16 overlap rule
chihminchao Aug 20, 2020
0f0fe68
Merge pull request #533 from chihminchao/rvv-fix-2020-08-20
aswaterman Aug 20, 2020
5f76a0d
Fix debug tests failing with impebreak enabled. (#530)
timsifive Aug 20, 2020
bfc2bea
rvv: remove quad instructions
chihminchao Aug 17, 2020
e11db4e
rf: remove bit extraction from processor.h
chihminchao Aug 17, 2020
eceda60
softfloat: add reciprocal api
chihminchao Aug 26, 2020
c9da294
rvv: add reciprocal instructions
chihminchao Aug 26, 2020
fa23a1c
rvv: check invalid frm for floating operations
chihminchao Aug 26, 2020
69fcd8d
rvv: trigger exp for illegal ncvt/wcvt eew
chihminchao Aug 26, 2020
6f7b46f
rvv: relax checking for vs1
chihminchao Aug 27, 2020
52b3eb9
rvv: disasm: fix whole load
chihminchao Aug 27, 2020
526b9ab
rvv: disasm: fix amo sub-opcode
chihminchao Aug 27, 2020
989f877
rvv: reading vcsr needs to enable mstatus.vs
chihminchao Aug 27, 2020
f974ce1
Merge pull request #535 from chihminchao/rvv-pre-1.0-2020-08-27
aswaterman Aug 31, 2020
3101b47
Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)
avpatel Sep 2, 2020
f398f0a
rvv: disasm: fix vamoadd name
chihminchao Sep 3, 2020
57fbf0e
rvv: disasm: separate vvm and vv
chihminchao Sep 8, 2020
ecc87c4
Merge pull request #542 from chihminchao/rvv-fix-2020-09-08
aswaterman Sep 8, 2020
58f23e1
Add MIP_MEIP to all_ints (#543)
abhinay-kayastha Sep 11, 2020
8957a8e
No need to catch illegal CSRs in set_csr
aswaterman Sep 15, 2020
a3376ff
Populate tval registers on illegal-/virtual-instruction traps
aswaterman Sep 15, 2020
3e7cba4
rvv: fix int type is not enough to do shift (#544)
HanKuanChen Sep 15, 2020
d6ac560
Don't throw virtual instruction exceptions for unimplemented CSRs
aswaterman Sep 21, 2020
fbb5a76
Fix polarity of hstatus.HU field
aswaterman Sep 21, 2020
ac46e18
Raise virtual-instruction traps correctly for WFI/SRET/SFENCE
aswaterman Sep 22, 2020
b1dc382
Don't error out if dlopen isn't available
aswaterman Sep 22, 2020
59d450e
Separate build of spike and spike-dasm
aswaterman Sep 22, 2020
4672cf2
Only install pkg-config files for libraries that are installed
aswaterman Sep 22, 2020
648e16e
Add basic continuous-integration flow
aswaterman Sep 22, 2020
b8832af
rvv: fix vfncvt/vfwcvt type checking
chihminchao Sep 11, 2020
0c60f10
rvv: commitlog: add peek parameter to get_csr
chihminchao Sep 23, 2020
43003ea
Merge pull request #550 from chihminchao/rvv-pre-1.0-2020-09-22
aswaterman Sep 23, 2020
77024fa
Fix priority of virtual vs. illegal instruction exceptions for HLV/HSV
aswaterman Sep 25, 2020
348fc0c
Fix priority of virtual vs. illegal instruction exceptions for HFENCE
aswaterman Sep 25, 2020
c6a5585
Correctly respect mstatus.TVM
aswaterman Sep 25, 2020
14ad0d9
Correctly respect mstatus.TSR
aswaterman Sep 25, 2020
9ac9ff2
correctly respect mstatus.TW and hstatus.VTW
aswaterman Sep 25, 2020
9d1fb48
pmp: fix local scope issue (#552)
chihminchao Sep 25, 2020
e7cdd75
Add core id to lines generated by --log-commits (#556)
sthiruva Sep 29, 2020
4baf970
Adding symbol lookup when --enable-commitlog is enabled (#558)
sthiruva Sep 29, 2020
0748aa4
Partially revert removal of .pc.in files; add disasm.pc.in
abhinay-kayastha Sep 29, 2020
ef3ea15
decode: only return meaningful bits for insn_t (#561)
chihminchao Oct 1, 2020
8966775
It should never be possible to select MPP=2
aswaterman Oct 4, 2020
b1d370c
Fix Mac OS build
aswaterman Oct 5, 2020
057a601
Update SATP and HGATP mask usage to make it clearer (#564)
abhinay-kayastha Oct 6, 2020
4bacf96
rvv: sstatus.SD needs to include vs dirty state (#563)
chihminchao Oct 6, 2020
77030fe
rvv: vamo needs to keep exception index in vstart
chihminchao Oct 6, 2020
f37ebac
rvv: commitlog: get hartid directly
chihminchao Oct 6, 2020
681fbac
rvv: remove elen >= max(xlen, flen) check
chihminchao Oct 5, 2020
f1c24ef
Merge pull request #565 from chihminchao/rvv-fix-2020-10-06
aswaterman Oct 6, 2020
72e5cab
Raise correct exception for counters when V=1
aswaterman Oct 9, 2020
e4419aa
Fix new ELF checks on big endian hosts (#567)
zeldin Oct 10, 2020
036aacb
reduce sig_len constraint to 4 bytes (#569)
neelgala Oct 16, 2020
be5af59
fixed mtval update for breakpoint instructions (#573)
neelgala Oct 17, 2020
06c434f
Update htif.cc (#577)
pawks Oct 22, 2020
70d7081
[riscv-bitmanip] Add bitmanip instructions
cliffordwolf Aug 11, 2019
98864d1
[riscv-bitmanip] Fix [un]shfl shamt length
cliffordwolf Aug 24, 2019
a4a2ce2
[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.91
cliffordwolf Aug 29, 2019
147aef1
[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.92
cliffordwolf Nov 8, 2019
672c50c
[riscv-bitmanip] Bugfixes in RV32B impl of CRC, SRO, [UN]SHFL
cliffordwolf Dec 6, 2019
2622def
[riscv-bitmanip] Add sh[123]add[u.w] instruction
cliffordwolf Dec 6, 2019
cab796f
Start adding B ext to disassembler
aswaterman Sep 18, 2020
d286140
Remove subu.w; change addu.w definition
aswaterman Oct 22, 2020
a06446f
Swap MAX and MINU encodings
aswaterman Oct 22, 2020
ec6ded4
Merge pull request #580 from riscv/riscv-bitmanip
aswaterman Oct 23, 2020
414c471
Fix trap generation in s2xlate()
avpatel Oct 24, 2020
47e17aa
Merge pull request #582 from avpatel/riscv_s2xlate_trap_fix_v1
aswaterman Oct 26, 2020
b2b6f45
Validate integer command-line arguments
aswaterman Oct 27, 2020
1af6708
commitlog: fix compilation warning
chihminchao Oct 22, 2020
30a45bb
rvv: check extra dst for index segment load
chihminchao Oct 22, 2020
1d30acb
Merge pull request #586 from chihminchao/rvv-fix-2020-10-26
aswaterman Oct 27, 2020
2a9849e
doc: update readme for bitmanip 0.92
kito-cheng Nov 3, 2020
641d7d0
Merge pull request #588 from kito-cheng/master
aswaterman Nov 3, 2020
8d09d84
Implement support for big-endian targets
zeldin Oct 11, 2020
ec2fd09
Update generated configure script
zeldin Oct 11, 2020
8e3bcb2
Tag target endian values to help guide conversion code
zeldin Oct 17, 2020
212249e
Allow fixed endianness to be observed through MBE/SBE/UBE
zeldin Oct 21, 2020
ad9bbf1
Make mmu_t::target_big_endian always available
zeldin Nov 7, 2020
6fe352d
Merge pull request #575 from zeldin/big-endian
aswaterman Nov 9, 2020
956ef9a
Update readme to reflect bi-endian support
aswaterman Nov 9, 2020
f019910
Make LR properly take misaligned exception
scottj97 Nov 11, 2020
e91092f
Use new require_alignment flag to simplify AMO check
scottj97 Nov 11, 2020
ad8ef88
mmu: add impl table and set function
chihminchao Nov 5, 2020
51b5702
mmu: extract common part of satp and vsatp setting
chihminchao Nov 5, 2020
bed716c
mmu: check mmu support
chihminchao Nov 5, 2020
0481b56
dts: extend dts api to get info of each cpu
chihminchao Nov 6, 2020
b675e0a
dts: mmu: parse mmu-type in dts
chihminchao Nov 6, 2020
9380375
Merge pull request #593 from chihminchao/selective-mmu-mode
aswaterman Nov 13, 2020
828d855
Merge pull request #592 from scottj97/fix-misaligned-lr
aswaterman Nov 13, 2020
70fdec9
Correct AMO exception cause for misaligned accesses (#594)
scottj97 Nov 13, 2020
0ca970d
dts: extract cpu node checking as helper function
chihminchao Nov 16, 2020
b4aa36c
dts: config pmp attribute by each core's setting
chihminchao Nov 16, 2020
77d8447
Merge pull request #598 from chihminchao/pmp-per-core
aswaterman Nov 16, 2020
a4994cb
Fix byteorder issues with struct riscv_stat (#596)
zeldin Nov 16, 2020
a081a01
Only use __builtin_expect for __GNUC__
aswaterman Nov 18, 2020
29178e6
Avoid use of __builtin_bswap for portability
aswaterman Nov 18, 2020
b2a2f24
Avoid use of __builtin_ctz for portability
aswaterman Nov 18, 2020
081bcad
Avoid use of __builtin_popcount for portability
aswaterman Nov 19, 2020
fce242a
Add Zsn extension
aswaterman Nov 19, 2020
ec00b9b
Invalid NAPOT settings cause page faults, not access exceptions
aswaterman Nov 19, 2020
e2e83c0
Don't include PTE.N bit as part of the PPN
aswaterman Nov 19, 2020
8be5c08
Fix VSSTATUS bits updation (#568)
avpatel Nov 23, 2020
a73e43f
Fix misaligned loads and stores for big endian target (#602)
zeldin Nov 24, 2020
d6cf0d2
Include stdexcept in ELF loader (#603)
db434 Nov 26, 2020
457f628
Fix hstatus.GVA and mstatus.GVA updation
avpatel Nov 27, 2020
d0d923e
Fix typo in HTVAL CSR write emulation
avpatel Nov 28, 2020
4b04d71
Merge pull request #605 from avpatel/riscv_gva_fix_v1
aswaterman Nov 30, 2020
f4f6e12
Fix #607: Add a core parameter to the interactive str command (#608)
hawkinsw Nov 30, 2020
0cb148a
Fix Issue #609 (#610)
hawkinsw Dec 1, 2020
6544804
Remove stray comma in configure
aswaterman Dec 1, 2020
21458a2
rvv: index load/store have benn separated into ordered and unordered …
chihminchao Dec 3, 2020
6d9617b
rvv: update the fractional lmul checking rule to rvv1.0-draft
davetw Dec 3, 2020
b8c05a2
rvv: check the vz/sext's eew
davetw Dec 3, 2020
a760df2
Merge pull request #613 from chihminchao/rvv-fix-2020-12-04
aswaterman Dec 4, 2020
d74b2cd
Oops...napot_bits should use ctz, not clz (#614)
daniellustig Dec 7, 2020
4e3d8df
Preserve abstract s0 write if progbuf excepts. (#615)
timsifive Dec 14, 2020
bf3a588
dts: mmu: replace 'riscv,bare' by 'riscv,sbare'
chihminchao Dec 14, 2020
e88a30c
disasm: show fench's predecessor and successor
chihminchao Dec 14, 2020
9224c93
rvv: fix the v[z|s]ext about elmul checking.
davetw Dec 7, 2020
790cfbc
Merge pull request #616 from chihminchao/misc-fix-2020-12-14
aswaterman Dec 15, 2020
236de4d
Add Zba/Zbb to disassembler
aswaterman Dec 16, 2020
11389c9
Check and use proc variable in MMU emulation
avpatel Dec 18, 2020
a8791f2
Update config file to support aarch64
mehmetoguzderin Dec 18, 2020
2aed3d2
Fix processor_t:take_interrupt() for HS-mode interrupts
avpatel Dec 18, 2020
3a7bc7d
Merge pull request #618 from avpatel/mmu_proc_fix_v1
aswaterman Dec 19, 2020
8deeb7d
Merge pull request #619 from mehmetoguzderin/guess-new-arch-2020
aswaterman Dec 19, 2020
4389996
If misaligned accesses are enabled, throw access fault on misaligned …
aswaterman Dec 19, 2020
032a68c
rvv: make fractional lmul checking simpler and stricter (#620)
chihminchao Dec 22, 2020
0f264a1
Install fesvr/byteorder.h to fix #622
aswaterman Dec 28, 2020
34de90b
Install config.h into include/fesvr
aswaterman Dec 29, 2020
29829bb
Fix compile warnings
aswaterman Dec 29, 2020
9671dc5
Add log2 helper function
aswaterman Dec 29, 2020
c14c1ab
Remove RV128 fmv.x.q/fmv.q.x instructions from disassembler
aswaterman Jan 9, 2021
c9af3eb
Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draft
aswaterman Jan 9, 2021
f1bcfac
Mention yum in addition to apt-get
aswaterman Jan 11, 2021
35d50bc
Add hypervisor extension to README
aswaterman Jan 14, 2021
9bfb43c
rvb: add xperm.[nbhw] (#629)
chihminchao Jan 18, 2021
5b51752
add support to page on demand (#634)
chihminchao Jan 21, 2021
ccdbfac
adding spike as a target to the arch-test-framework (#630)
neelgala Jan 21, 2021
d6238d9
scalar-crypto: Initial spike support for v0.8.1 (#635)
ben-marshall Jan 22, 2021
ad94207
Increment minstret when WFI completes (#636)
scottj97 Jan 28, 2021
60f7eda
fixed typos and paths for arch_test readme (#638)
neelgala Feb 2, 2021
f8fc5d8
fix logging for fcsr (#639)
neelgala Feb 4, 2021
716245f
Fix --kernel and --initrd options w.r.t. sparse mem_t implementation
aswaterman Feb 4, 2021
d7200bf
Fix compile errors
aswaterman Feb 4, 2021
86ab921
Refactor headers
aswaterman Feb 4, 2021
3887f46
Zsn has been renamed Svnapot (#641)
daniellustig Feb 8, 2021
51e718c
Fix commit log for WFI instructions
aswaterman Feb 10, 2021
3d19864
Support multiple extensions at the same time
zitaofang Feb 14, 2021
b167bbd
fix require fp since spec said <When V=1, both vsstatus.FS and the HS…
francis4096 Feb 17, 2021
142a3bb
Fix Guest/VM and Host extension status sync-up
avpatel Feb 17, 2021
6111fdd
Fix require_vector_vs() for H-extension
avpatel Feb 17, 2021
8faa928
Merge pull request #647 from avpatel/guest_ext_status_fix_v1
aswaterman Feb 17, 2021
5730d12
scalar-crypto: Fix RV32 sha512 instructions.
ben-marshall Feb 18, 2021
da7748e
scalar-crypto: Fix decoding of RV64 AES instructions.
ben-marshall Feb 18, 2021
15f8430
rvv: disas: reserved sew >= 128
chihminchao Feb 22, 2021
487f1b7
rvv: rename sqrt/reciprocal instructions
chihminchao Feb 22, 2021
60428fc
rvv: add vse1/vle1
chihminchao Feb 22, 2021
45b8948
rvv: totally remove ediv
chihminchao Feb 23, 2021
a9eae3e
rvv: add vsetivli
chihminchao Feb 23, 2021
12748b5
rvv: update readme
chihminchao Feb 23, 2021
9bfa094
Merge pull request #655 from chihminchao/rvv-v0.10
aswaterman Feb 26, 2021
fbb4645
Correct RV64 vsstatus.UXL field (#659)
scottj97 Mar 1, 2021
f62660a
Fix AMO guest page fault as store guest fault (#663)
francis4096 Mar 3, 2021
1212919
Hard-wire VSXL field in RV64 hstatus (#664)
scottj97 Mar 3, 2021
0cd5a8b
Fix bug where CSRW to vsstatus would not set SD correctly (#665)
scottj97 Mar 4, 2021
3f27fd4
Merge branch 'master' of https://github.com/riscv/riscv-isa-sim
zitaofang Mar 5, 2021
323a93e
Fix hedeleg to match Privileged Spec requirements (#669)
scottj97 Mar 5, 2021
53d94b1
Don't make MPRV load/store virtual if MPV=1, MPP=3 (#666)
jameshippisley Mar 5, 2021
619b5f9
Fix bug where hstatus.SPVP was being changed when it should not be (#…
scottj97 Mar 6, 2021
853320f
Fix vsstatus.FS misbehavior (#661)
scottj97 Mar 6, 2021
6d5a351
Forbid `csrw vsstatus` from modifying the UXL field (#671)
scottj97 Mar 8, 2021
06f630c
Merge pull request #649 from ben-marshall/scalar-crypto-fix
aswaterman Mar 8, 2021
1969ab2
Fix ifdef
zitaofang Mar 9, 2021
16a654d
Stylistic changes
aswaterman Mar 11, 2021
5c1b086
Fixed vsetvl conflict
zitaofang Mar 11, 2021
b0eee7f
Merge branch 'master' of https://github.com/riscv/riscv-isa-sim into …
zitaofang Mar 11, 2021
8feafa0
Fixed vsetvl conflict #2
zitaofang Mar 11, 2021
a31ac28
Fix and refactor RV32-only and RV64-only instruction handling
aswaterman Mar 11, 2021
da5866e
HS-level interrupts should always be enabled when in VS-mode
scottj97 Mar 23, 2021
634b7eb
Merge pull request #680 from scottj97/fix-vs-interrupts
aswaterman Mar 24, 2021
c0cd8a6
Add `statx` syscall
huaixv Mar 25, 2021
3caa6e4
Merge pull request #681 from huaixv/master
aswaterman Mar 25, 2021
b65ead8
Fix Ubuntu 16.04 build
aswaterman Mar 25, 2021
4403fae
Fix xperm.[bhn] on RV32
aswaterman Mar 25, 2021
eee2e32
Fix `stx_ino` member name in commit b65ead8
huaixv Mar 26, 2021
2132af1
Fix statx configure check
aswaterman Mar 26, 2021
4e14e98
Merge pull request #683 from huaixv/master
aswaterman Mar 26, 2021
21684fd
Add missing require_rv64 for rv64-only insns. (#684)
marcfedorow Mar 26, 2021
6c18ef5
replace old compliance name with new arch-test name in spike target R…
allenjbaum Apr 6, 2021
9d4f45c
Display 32 bits (#693)
emelcher Apr 13, 2021
3bda10d
Implement JTAG BYPASS register. (#697)
timsifive Apr 27, 2021
dbd59e9
Fix compiler warning (#706)
jmonesti May 1, 2021
159a19f
Improve coding style of logging printfs
aswaterman May 1, 2021
71acc77
in get_csr, use ret macro instead of return statement
aswaterman May 9, 2021
0981d39
Support RISC-V p-ext-proposal v0.9.2 (#637)
hope51607 May 11, 2021
b673537
Enforce hgatp WARLness in concordance with the spec
aswaterman May 17, 2021
ce170a7
Implement satp/vsatp WARLness correctly
aswaterman May 17, 2021
4630011
Don't raise virtual instruction exceptions writes to read-only registers
aswaterman May 20, 2021
e2691f0
Add alignment check for lr instruction (#713)
zhongchengyong May 25, 2021
1c52121
Add multiple extension support to the bump
zitaofang May 25, 2021
6252677
Fix CSR read-only check regression introduced in 463001198
aswaterman Jun 2, 2021
16308bc
Fix ambiguous if/else warning
aswaterman Jun 2, 2021
cb7805a
Accept Zba, Zbb, Zbc, Zbs ISA strings
aswaterman Jun 2, 2021
bf4b1e0
Remove Duff's Device in main simulation loop (#721)
aswaterman Jun 2, 2021
3270841
pmp: mstatus.mprv should be clear if mpp is not M-mode
chihminchao Apr 16, 2021
d99db79
sim: rewrite memory-region overlapping helper
chihminchao Apr 20, 2021
3dc70c4
sim: fix multiple x extension issue
chihminchao Apr 22, 2021
2f82110
Remove hvsetvl
zitaofang Jun 4, 2021
88c223f
Merge branch 'master' of github.com:ucb-bar/esp-isa-sim into feb2021-…
zitaofang Jun 4, 2021
57e88c7
encoding: udpate and move platform-related define out
chihminchao Jun 3, 2021
9d91c7a
rvv: vdot has been removed
chihminchao Jun 4, 2021
7fa7a20
Merge pull request #699 from chihminchao/misc-fix-2021-04-21
aswaterman Jun 4, 2021
facb985
scalar-crypto: Encoding fixes for v0.9.2
ben-marshall Jun 4, 2021
1621807
Merge pull request #722 from ben-marshall/scalar-crypto-v0.9.2
aswaterman Jun 4, 2021
83bebdc
Move SHA3 to esp-tools
zitaofang Jun 5, 2021
6c758c8
Merge branch 'master' of https://github.com/riscv/riscv-isa-sim into …
zitaofang Jun 6, 2021
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2 changes: 2 additions & 0 deletions .github/workflows/apt-packages.txt
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@@ -0,0 +1,2 @@
build-essential
device-tree-compiler
28 changes: 28 additions & 0 deletions .github/workflows/continuous-integration.yml
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# This file describes the GitHub Actions workflow for continuous integration of Spike.
#
# See
# https://help.github.com/en/actions/reference/workflow-syntax-for-github-actions
# for API reference documentation on this file format.

name: Continuous Integration

on:
push:
branches:
- master
pull_request:
branches:
- master


jobs:
test:
name: Test Spike build
runs-on: ubuntu-20.04
steps:
- uses: actions/checkout@v2

- name: Install Dependencies
run: sudo xargs apt-get install -y < .github/workflows/apt-packages.txt

- run: ci-tests/test-spike
18 changes: 14 additions & 4 deletions Makefile.in
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ src_dir := @srcdir@
scripts_dir := $(src_dir)/scripts

HAVE_INT128 := @HAVE_INT128@
HAVE_DLOPEN := @HAVE_DLOPEN@

# If the version information is not in the configure script, then we
# assume that we are in a working directory. We use the vcs-version.sh
Expand Down Expand Up @@ -242,7 +243,7 @@ $(2)_lib_libnames_shared := $$(if $$($(2)_install_shared_lib),lib$(1).so,)

lib$(1).a : $$($(2)_objs) $$($(2)_c_objs) $$($(2)_lib_libnames)
$(AR) rcs $$@ $$^
lib$(1).so : $$($(2)_objs) $$($(2)_c_objs) $$($(2)_lib_libnames) $$($(2)_lib_libnames_shared)
lib$(1).so : $$($(2)_objs) $$($(2)_c_objs) $$($(2)_lib_libnames_shared) $$($(2)_lib_libnames)
$(LINK) -shared -o $$@ $(if $(filter Darwin,$(shell uname -s)),-install_name $(install_libs_dir)/$$@) $$^ $$($(2)_lib_libnames) $(LIBS)

$(2)_junk += lib$(1).a
Expand Down Expand Up @@ -334,11 +335,12 @@ deps += $$($(2)_deps)

test_outs += $$($(2)_test_outs)

install_config_hdrs += $$(if $$($(2)_install_config_hdr),$(1),)
install_hdrs += $$(addprefix $(src_dir)/$(1)/, $$($(2)_install_hdrs))
install_libs += $$(if $$($(2)_install_lib),lib$(1).a,)
install_libs += $$(if $$($(2)_install_shared_lib),lib$(1).so,)
install_exes += $$($(2)_install_prog_exes)
install_pcs += riscv-$(1).pc
install_pcs += $$(if $$($(2)_install_lib),riscv-$(1).pc,)

endef

Expand Down Expand Up @@ -381,6 +383,14 @@ check : check-cpp check-bin
# Installation
#-------------------------------------------------------------------------

install-config-hdrs : config.h
$(MKINSTALLDIRS) $(install_hdrs_dir)
for dir in $(install_config_hdrs); \
do \
$(MKINSTALLDIRS) $(install_hdrs_dir)/$$dir; \
$(INSTALL_HDR) $< $(install_hdrs_dir)/$$dir; \
done

install-hdrs : $(install_hdrs)
$(MKINSTALLDIRS) $(install_hdrs_dir)
for file in $(subst $(src_dir)/,,$^); \
Expand Down Expand Up @@ -410,9 +420,9 @@ install-pc : $(install_pcs)
$(INSTALL_HDR) $$file $(install_libs_dir)/pkgconfig/; \
done

install : install-hdrs install-libs install-exes install-pc
install : install-hdrs install-config-hdrs install-libs install-exes install-pc

.PHONY : install install-hdrs install-libs install-exes
.PHONY : install install-hdrs install-config-hdrs install-libs install-exes

#-------------------------------------------------------------------------
# Regenerate configure information
Expand Down
11 changes: 10 additions & 1 deletion README.md
Original file line number Diff line number Diff line change
Expand Up @@ -18,9 +18,15 @@ Spike supports the following RISC-V ISA features:
- D extension, v2.2
- Q extension, v2.2
- C extension, v2.0
- V extension, v0.8, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_)
- B extension, v0.92
- K extension, v0.8.1 ([Scalar Cryptography](https://github.com/riscv/riscv-crypto))
- V extension, v0.10, w/ Zvlsseg/Zvamo (_requires a 64-bit host_)
- P extension, v0.9.2
- Bi-endianness
- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
- Machine, Supervisor, and User modes, v1.11
- Hypervisor extension, v0.6.1
- Svnapot extension, v0.1
- Debug v0.14

Versioning and APIs
Expand Down Expand Up @@ -52,6 +58,9 @@ install path.
$ make
$ [sudo] make install

If your system uses the `yum` package manager, you can substitute
`yum install dtc` for the first step.

Build Steps on OpenBSD
----------------------

Expand Down
25 changes: 25 additions & 0 deletions arch_test_target/spike/Makefile.include
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
export TARGETDIR ?= /scratch/git-repo/github/neel/riscv-isa-sim/arch_test_target

# set XLEN to max supported XLEN. Allowed values are 32 and 64
export XLEN ?= 64

# name of the target. Note a folder of the same name must exist in the TARGETDIR directory
export RISCV_TARGET ?= spike

# set the RISCV_DEVICE environment to a single extension you want to compile, simulate and/or verify.
# Leave this blank if you want to iterate through all the supported extensions available in the target
export RISCV_DEVICE ?=

# set this to a string which needs to be passed to your target Makefile.include files
export RISCV_TARGET_FLAGS ?=

# set this if you want to enable assertions on the test-suites. Currently no tests support
# assertions.
export RISCV_ASSERT ?= 0

# set the number of parallel jobs (along with any other arguments) you would like to execute. Note that the target needs to ensure
# that no common files across jobs are created/overwritten leading to unknown behavior
JOBS= -j1


58 changes: 58 additions & 0 deletions arch_test_target/spike/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
# Using the Spike Simulator as an Architectural test model

This is a reference for running Spike as a target for the RISC-V Architectural Test framework.

## Getting Spike

The Spike repository should be cloned from [here](https://github.com/riscv/riscv-isa-sim/), preferably at the same directory level as the riscv-arch-test repository.

## Building Spike

The [README.md](../README.md) at the top level of the riscv-isa-sim directory gives details on building an executable spike model.

## Adding Spike as a target to the Architectural Test framework

Also at the top level is an ``arch_test_target directory``. This directory contains all the collaterals
required to add Spike as a target to the architectural test framework.

The file ``arch_test_target/spike/Makefile.include`` contains various parameters which can be set by
the user to modify the instance of spike on which the tests need to be run.
The user can modify the ``XLEN`` variable based on whether 32-bit or 64-bit tests need to be run.
If one would like to run tests of a single extension then set the `RISCV_DEVICE` to that extension
name (eg. M, C, Zifencei, etc). Leaving the ``RISCV_DEVICE`` empty would indicate running all tests
for all extensions available in the ``device/rv{XLEN}i_m`` directory No other variables should be modified.

Now clone the architectural test framework repo and copy the updated Makefile.include to it:

```
$ git clone https://github.com/riscv/riscv-arch-test.git
$ cd riscv-arch-test
$ cp <custom-path>/riscv-isa-sim/arch_test_target/Makefile.include .
```

The user will have to modify the ``TARGETDIR`` variable in ``riscv-arch-test/Makefile.include`` to point to the
absolute location of the ``riscv-isa-sim/arch_test_target`` directory.

You can execute the tests from the root directory of the riscv-arch-test repo:

```
make compile simulate verify
```

## Updating the target for new tests

As tests for new extensions are added to the architectural test repo, the spike target (i.e.
arch_test_target directory) will also need to be updated accordingly. Please refer to the [Porting a new target](https://github.com/riscv/riscv-arch-test/blob/master/doc/README.adoc#5-porting-a-new-target)
section for more details on what those changes/updates should be.












40 changes: 40 additions & 0 deletions arch_test_target/spike/device/rv32i_m/C/Makefile.include
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
TARGET_SIM ?= spike
TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
$(error Target simulator executable '$(TARGET_SIM)` not found)
endif

RISCV_PREFIX ?= riscv32-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)

COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
-I$(ROOTDIR)/riscv-test-suite/env/ \
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
$$(<) -o $$@
OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
$$(RISCV_OBJDUMP) $$@ --source > [email protected]


COMPILE_TARGET=\
$(COMPILE_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ; \
$(OBJ_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ;

RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ic \
+signature=$(*).signature.output +signature-granularity=4\
$<

RUN_TARGET=\
$(RUN_CMD)
40 changes: 40 additions & 0 deletions arch_test_target/spike/device/rv32i_m/I/Makefile.include
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
TARGET_SIM ?= spike
TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
$(error Target simulator executable '$(TARGET_SIM)` not found)
endif

RISCV_PREFIX ?= riscv32-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)

COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
-I$(ROOTDIR)/riscv-test-suite/env/ \
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
$$(<) -o $$@
OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
$$(RISCV_OBJDUMP) $$@ --source > [email protected]


COMPILE_TARGET=\
$(COMPILE_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ; \
$(OBJ_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ;

RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \
+signature=$(*).signature.output +signature-granularity=4\
$<

RUN_TARGET=\
$(RUN_CMD)
40 changes: 40 additions & 0 deletions arch_test_target/spike/device/rv32i_m/M/Makefile.include
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
TARGET_SIM ?= spike
TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
$(error Target simulator executable '$(TARGET_SIM)` not found)
endif

RISCV_PREFIX ?= riscv32-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)

COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
-I$(ROOTDIR)/riscv-test-suite/env/ \
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
$$(<) -o $$@
OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
$$(RISCV_OBJDUMP) $$@ --source > [email protected]


COMPILE_TARGET=\
$(COMPILE_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ; \
$(OBJ_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ;

RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32im \
+signature=$(*).signature.output +signature-granularity=4\
$<

RUN_TARGET=\
$(RUN_CMD)
40 changes: 40 additions & 0 deletions arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
TARGET_SIM ?= spike
TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
$(error Target simulator executable '$(TARGET_SIM)` not found)
endif

RISCV_PREFIX ?= riscv32-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)

COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
-I$(ROOTDIR)/riscv-test-suite/env/ \
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
$$(<) -o $$@
OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
$$(RISCV_OBJDUMP) $$@ --source > [email protected]


COMPILE_TARGET=\
$(COMPILE_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ; \
$(OBJ_CMD); \
if [ $$$$? -ne 0 ] ; \
then \
echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
exit 1 ; \
fi ;

RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \
+signature=$(*).signature.output +signature-granularity=4\
$<

RUN_TARGET=\
$(RUN_CMD)
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