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Releases: schang412/cocotbext-spi

v0.5.0

02 Nov 13:20
8ecd79b
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What's Changed

  • feat: make SpiBus signals names more flexible by @AJacquin in #21

New Contributors

Full Changelog: v0.4.0...v0.5.0

v0.4.0

05 Oct 17:56
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  • BREAKING feature: replaced SpiSignals with SpiBus to follow cocotb-bus conventions
  • feature: allow burst transmits from the master
  • fix: error in master.write() documentation
  • feature: added ADI ADXL345 device

Known Issues:

  • different behavior for different simulators (icarus, incisive, and verilator)
  • verilator behaves strangely with new SpiBus

v0.3.2

25 Feb 22:48
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  • Fix bug with __all__ import
  • Test automatic release pipeline

0.3.1

25 Feb 20:40
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Notable Changes in this Release:

  • Fix bug resulting in incompatibility with Python 3.7
  • Use pdm to facilitate packaging and distribution
  • Add flake8 linter for code

0.3.0

09 Feb 20:00
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Notable changes in this Release:

  • Bug Fixes
  • Add feature to ignore certain rx values in the master (not replicated in slave because implementation of slave is up to user)
  • Switch to pyproject.toml and automatic versioning

0.2.0

30 Mar 17:37
9b32f50
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Notable changes in this release:

  • Changed the timing for SPI signals for both master and slave.
    • Previously, ignored falling edges if a rising edge has not yet been seen. CPHA=0 indicates sample on rising edge, irrespective of idle clock polarity. This followed Analog Devices Timing Diagrams.
    • Currently, CPHA=0 indicates sample on the first edge of sclk and write on the second. This is compliant with more vendors and matches the Wikipedia definition of the SPI modes.

0.1.2

18 Jan 19:23
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Fixed SPI clocking for SPI modes 1,2,4.

0.1.1

11 Aug 03:11
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Fixed bug in spi_master where the first bit wasn't being processed correctly.

0.1.0

29 Jul 07:39
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Initial Release