add pre-commit to project

.gitignore

@@ -19,4 +19,4 @@ tests/**/.pytest_cache
 *~
 
 cocotbext/spi/_version.py
-.pdm.toml
+.pdm.toml

.pre-commit-config.yaml

@@ -0,0 +1,24 @@
+# See https://pre-commit.com for more information
+# See https://pre-commit.com/hooks.html for more hooks
+repos:
+-   repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: v3.2.0
+    hooks:
+    -   id: trailing-whitespace
+    -   id: end-of-file-fixer
+    -   id: check-yaml
+    -   id: check-added-large-files
+    -   id: debug-statements
+-   repo: https://github.com/PyCQA/flake8
+    rev: 6.0.0
+    hooks:
+    -   id: flake8
+-   repo: https://github.com/asottile/pyupgrade
+    rev: v3.3.1
+    hooks:
+    -   id: pyupgrade
+        args: [--py37-plus]
+-   repo: https://github.com/tox-dev/pyproject-fmt
+    rev: "0.8.0"
+    hooks:
+    -   id: pyproject-fmt

COPYING

@@ -16,4 +16,4 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
+THE SOFTWARE.

MANIFEST.in

@@ -1,4 +1,3 @@
 include LICENSE
 include README.md
 recursive-include tests Makefile test_*.py test_*.v
-

README.md

@@ -1,6 +1,8 @@
 # SPI Interface for Cocotb
 
 [![Regression Tests](https://github.com/schang412/cocotbext-spi/actions/workflows/regression-tests.yml/badge.svg)](https://github.com/schang412/cocotbext-spi/actions/workflows/regression-tests.yml)
+[![pdm-managed](https://img.shields.io/badge/pdm-managed-blueviolet)](https://pdm.fming.dev)
+[![pre-commit](https://img.shields.io/badge/pre--commit-enabled-brightgreen?logo=pre-commit)](https://github.com/pre-commit/pre-commit)
 
 GitHub repository: https://github.com/schang412/cocotbext-spi
 
@@ -62,7 +64,7 @@ spi_config = SpiConfig(
     cpol       = False,    # clock idle polarity
     cpha       = True,     # clock phase (CPHA=True means data sampled on second edge)
     msb_first  = True,     # the order that bits are clocked onto the wire
-    data_output_idle = 1,  # the idle value of the MOSI or MISO line 
+    data_output_idle = 1,  # the idle value of the MOSI or MISO line
     frame_spacing_ns = 1,  # the spacing between frames that the master waits for or the slave obeys
                            #       the slave should raise SpiFrameError if this is not obeyed.
     ignore_rx_value = None # MISO value that should be ignored when received

cocotbext/spi/spi.py

@@ -86,7 +86,7 @@ def __init__(self, signals, config):
 
         self._sclk.setimmediatevalue(int(self._config.cpol))
         self._mosi.setimmediatevalue(self._config.data_output_idle)
-        self._cs.setimmediatevalue((1 if self._cs_active_low else 0))
+        self._cs.setimmediatevalue(1 if self._cs_active_low else 0)
 
         self._SpiClock = _SpiClock(signal=self._sclk,
                                    period=(1 / self._config.sclk_freq),

pyproject.toml

@@ -1,27 +1,36 @@
 [build-system]
-requires = ["setuptools>=61", "wheel", "setuptools_scm[toml]>=6.2"]
 build-backend = "setuptools.build_meta"
+requires = [
+  "setuptools>=61",
+  "setuptools_scm[toml]>=6.2",
+  "wheel",
+]
 
 [project]
 name = "cocotbext-spi"
 description = "SPI modules for cocotb"
+readme = "README.md"
+license = {text = "MIT"}
 authors = [
     {name = "Spencer Chang", email = "[email protected]"},
 ]
-dependencies = [
-    "cocotb>=1.6",
-]
+requires-python = ">=3.7"
 classifiers = [
     "Development Status :: 3 - Alpha",
     "Programming Language :: Python :: 3",
     "License :: OSI Approved :: MIT License",
     "Operating System :: OS Independent",
     "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
 ]
-requires-python = ">=3.7"
-readme = "README.md"
-license = {text = "MIT"}
-dynamic = ["version"]
+dynamic = [
+  "version",
+]
+dependencies = [
+  "cocotb>=1.6",
+]
+[project.urls]
+repository = "https://github.com/schang412/cocotbext-spi"
+
 
 [tool.setuptools_scm]
 write_to = "cocotbext/spi/_version.py"
@@ -32,27 +41,6 @@ testpaths = [
 ]
 addopts = "--import-mode importlib"
 
-[tool.tox]
-legacy_tox_ini = """
-[tox]
-isolated_build = true
-envlist = py{37,38,39},lint
-
-[testenv]
-setenv =
-    PDM_IGNORE_SAVED_PYTHON="1"
-deps = pdm
-commands =
-    pdm install --dev
-    pytest tests -n auto
-
-[testenv:lint]
-deps = pdm
-commands =
-    pdm install -G lint
-    flake8 cocotbext/ tests/
-"""
-
 [tool.pdm]
 [tool.pdm.dev-dependencies]
 test = [

tests/spi/Makefile

@@ -35,4 +35,4 @@ iverilog_dump.v:
 clean::
 	@rm -rf iverilog_dump.v
 	@rm -rf dump.fst $(TOPLEVEL).fst
-	@rm -rf results.xml
+	@rm -rf results.xml

tests/spi/test_spi.py

@@ -91,7 +91,7 @@ async def run_test(dut, payload_lengths, payload_data, word_width=16, spi_mode=1
         filtered_sink = [sink_content] if sink_content != ignore_rx_value else []
 
         tb.log.info("Read data: %s", ','.join(['0x%02x' % x for x in rx_data]))
-        tb.log.info("In register: 0x{:02x}".format(sink_content))
+        tb.log.info(f"In register: 0x{sink_content:02x}")
         assert list(rx_data[1:]) + filtered_sink == filtered_test_data
 
     await Timer(100, 'us')

tests/spi_devices/TI/ads8028/Makefile

@@ -35,4 +35,4 @@ iverilog_dump.v:
 clean::
 	@rm -rf iverilog_dump.v
 	@rm -rf dump.fst $(TOPLEVEL).fst
-	@rm -rf results.xml
+	@rm -rf results.xml

tests/spi_devices/TI/ads8028/test_ads8028.v

@@ -8,4 +8,4 @@ module test_ads8028
     inout wire ncs
 );
 
-endmodule // test_ads8028
+endmodule // test_ads8028

tests/spi_devices/TI/drv8304/Makefile

@@ -35,4 +35,4 @@ iverilog_dump.v:
 clean::
 	@rm -rf iverilog_dump.v
 	@rm -rf dump.fst $(TOPLEVEL).fst
-	@rm -rf results.xml
+	@rm -rf results.xml

tests/spi_devices/TI/drv8304/test_drv8304.py

@@ -1,4 +1,3 @@
-
 """
 Copyright (c) 2021 Spencer Chang
 

tests/spi_devices/TI/drv8304/test_drv8304.v

@@ -8,4 +8,4 @@ module test_drv8304
     inout wire ncs
 );
 
-endmodule // test_drv8304
+endmodule // test_drv8304

tests/spi_devices/Trinamic/tmc4671/Makefile

@@ -35,4 +35,4 @@ iverilog_dump.v:
 clean::
 	@rm -rf iverilog_dump.v
 	@rm -rf dump.fst $(TOPLEVEL).fst
-	@rm -rf results.xml
+	@rm -rf results.xml

tests/spi_devices/Trinamic/tmc4671/test_tmc4671.v

@@ -8,4 +8,4 @@ module test_tmc4671
     inout wire ncs
 );
 
-endmodule // test_tmc4671
+endmodule // test_tmc4671

tox.ini

@@ -0,0 +1,29 @@
+[tox]
+isolated_build = true
+envlist = py{37,38,39},lint,check-dist
+
+[flake8]
+max-line-length = 120
+
+[testenv]
+setenv =
+    PDM_IGNORE_SAVED_PYTHON="1"
+deps = pdm
+commands =
+    pdm install --dev
+    pytest tests -n auto
+
+[testenv:lint]
+deps = pdm
+commands =
+    pdm install -G lint
+    flake8 cocotbext/ tests/
+
+[testenv:check-dist]
+skip_install = true
+deps =
+    pdm
+    twine
+commands =
+    pdm build
+    twine check dist/*