Skip to content

0.2.0
Compare
Choose a tag to compare
@schang412 schang412 released this 30 Mar 17:37
· 20 commits to main since this release
v0.2.0
9b32f50
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.

Notable changes in this release:

  • Changed the timing for SPI signals for both master and slave.
    • Previously, ignored falling edges if a rising edge has not yet been seen. CPHA=0 indicates sample on rising edge, irrespective of idle clock polarity. This followed Analog Devices Timing Diagrams.
    • Currently, CPHA=0 indicates sample on the first edge of sclk and write on the second. This is compliant with more vendors and matches the Wikipedia definition of the SPI modes.
Assets 4
Loading