v0.12.0-esp32-20241016

Features:

• flash: Added esp32c61 flash support.
• target/esp32c5: Added reset reason logging.
• target/esp32c61: Added reset reason logging.
• target/esp32p4: Added TCM memory as a valid memory region.
• target/espressif: Added support for printing names of extended Espressif syscalls set in the log.

Bug fixes:

• target/riscv: Call target reset handler for also resets initiated outside of OpenOCD. Previously it was called only for resets initiated by OpenOCD itself.
  Therefore reset reasons were not printed when target is reset by HW signal or via SW reset initiated due to the panic.
• target/esp32p4: Invalidate L1 ICache after writing the memory to fix the SW breakpoint miss issue.
• target/esp_riscv: Halt other cores before running bp/wp set commands. Could lead to missing bp/wp hits by other core which were running at the moment of that semihosting call.
• target/esp_riscv: Avoid apptrace data polling during reset cycle.
• tcl/esp_riscv: Configure default riscv settings for each core. Previosuly some config options were applied to the first core only.
• target/esp_riscv: Clear WDT interrupt states when the target is halted. That could lead to spontaneous interrupt WDT panics during step/continue.
• target/esp_riscv: Avoid false floating point instruction faults which are normal and handled by panic code in IDF.
• target/esp_riscv: Filter out interrupts and report exceptions reasons only.
• tcl/esp_common: Added missing global variable in configure_esp_xtensa_default_settings TCL function.

Other:

• Synchronized with upstream.

v0.12.0-esp32-20240821

Features:

• target/espressif: Added esp32c61 initial support.
• tools: Added script to detect Espressif devkits connected to the host.

Bug fixes:

• tcl/espressif: Clear breakpoints before shutdown openocd. When openocd gets the shutdown signal, it first executes shutdown commands. After that, invokes the gdb_detach event callbacks. This is fine for the xtensa but for the riscv, command order is important. Because we will disable the DM within the shutdown command.
• target/espressif: Fix add & remove lazy breakpoint process. The bug could lead to the condition when not all breakpoints are processed (added/removed).

Other:

• target/espressif: Added command to disable lazy breakpoints. This could help to workaround problems with lazy breakpoints handling.

v0.12.0-esp32-20240726

Features:

• target/espressif: Added base debugging support for ESP32-C5.
• target/esp32c5: Added flash support.
• target/esp32c6: Add LP core debugging support. Added special config file for debugging HP + LP cores as two HW threads.
• target/espressif: Added esp32p4 smp config.
• target/espressif: Added batch process for flash breakpoints. Now to set/clear flash breakpoints stub is loaded to target memory only once upon target resume/halt. This improves debugging speed significantly.
• flash/espressif: Added support to use stub which is built into target application binary, so there is no need to load it every time flash breakpoint needs to be set/clered. This improves debugging speed significantly.
• target/esp_riscv: Added mideleg, medeleg, mie and mip regs to the esp32c6 and esp32h2 register list.
• target/esp32p4: Enabled debug assist monitor support.
• target/esp_riscv: Added floating point registers to the register list.
• target/espressif: Add RISCV read only regs (mvendorid, marchid, mimpid, mhartid) to the register list.
• rtos/zephyr: Added thread awareness for esp32, esp32s3 and RISCV.
• target/espressif: The algorithm timeout has been decreased from 40 seconds to 3 seconds.

Bug fixes:

• rtos/freertos: Fixed ESP32-P4 reset after cleaning memory in FreeRTOS post reset handler.
• contrib/loaders: Fixed esp32s3 flash init sequence. This led to flash probe failure for octal flash chips IDF app is built w/o PSRAM support.
• rtos/FreeRTOS: Fixed unknown symbol read errors on Amazon FreeRTOS SMP version.
• target/espressif: Fixed apptrace init error on riscv chips. During apptrace init, reading invalid memory caused an issue on some riscv targets such as esp32c2 and esp32p4.
• target/espressif: Fix smp flash command handlers. They were not working properly for the 2nd core, leading an error when running the appimage_offset or stub_log commands
• loaders/esp: Fixed dynamic mmu page size issue. With the 2MB flash config, the stub flasher could not properly configure the Cache MMU, so mapping and flash breakpoints were not working.
• target/riscv: Fixed handling external reset in halted state. Previously it led to busy timeout errors.
• target/esp_riscv: Added pre-shutdown command to ensure that debug module is deactivated before exit.
• target/riscv: Increased dm idle_count by dtmcs.idle. Make OpenOCD using dtmcs.idle value to decide how long stay in RunTest/Idle state during dmi_scan.
• jtag/esp_usb_jtag: Re-init usb port when replug or hard reset detected. On Windows, libusb_reset() is not functional. Libusb prints the error AbortPipe (pipe address 02) failed: [22] The device does not recognize the command and returns with a success code. So, OpenOCD still thinks that the revive_device has been completed successfully. But still, continue to get write_error from the endpoint.

Other:

• Added win64 package

v0.12.0-esp32-20240318

Features:

• target/esp32p4: Added flasher support.
• target/esp32p4: Added custom registers support.
• tcl/board: Added ESP32-P4 config files.
• rtos/FreeRTOS: Added ESP32-P4 support.

Bug fixes:

• flash/esp: Fixed storing of a vaddr as a paddr for DROM flash bank. Close #318.
• Some typo fixes regarding ESP / RiscV files. Close #314.
• rtos/nuttx: Added sanity checks during thread updates. Added checks for the values read from target.
• target/esp32p4: Fixed max hw bp/wp nums.
• target/esp32p4: Fixed soc reset function.
• target/esp32p4: Writeback cache before memory read/write. While halted memory access works fine with the help of fence instruction, runtime memory reads returned garbage values. The issue is resolved by performing cache synchronization before memory read/write operations.
• target/esp_riscv: Ensure reading/writing aligned memory address. SBA access requires 4 byte alignment.
• target/esp: Avoided reading invalid apptrace config addresses. We may read mem_cfg_addr as zero, when target algorithm code is not running yet. For some targets (e.g. esp32p4), reading invalid address will be an error.
• contrib/loaders/flash/esp: Fixed last data chunk padding when writing to flash. This could cause to attempt to write beyond flash boundaries.
• flash/nor/esp: Fixed target endianess handling for flash mappings structs.
• flash/esp_xtensa: Removed limitation for accessing lower flash addresses. Removes SW limitation for writing flash 0x1000 for ESP32 and ESP32-S2.
• flash/nor: Fixed handling of zero-size flash chips in get_flash_bank_by_addr. Led to assertion failure when ESP virtual flash banks have zero size, e.g. there is no app image in flash, so flah mappings are not available.

Other:

• rtos/nuttx: Updated TCB structure for the recent Nuttx changes.
• target/esp32p4: Reordered mem access to better cache handling.
• loaders/espressif: Added license info to the flasher stub headers.
• tcl/target: Renamed ESP32_ONLYCPU with ESP_ONLYCPU TCL config variable.
• tcl/target: Added esp_gcov wrapper TCL functions for esp gcov command.
• flash/esp: Avoided probing flash bank for simple flash/flasher config commands.
• Synchronized with upstream

v0.12.0-esp32-20230921

Features:

• target/esp32p4: Added ESP32-P4 target support. Basic debugging functionality without flash support is now available.
• target/esp32{c2,c3,h2,c6}: Exposed custom CSRs for RISC-V targets.
• target/esp32{h2,c6}: Added memory protection support.
• target/espressif: Added support to print details for abort(), assert() and pseudo exception reasons.
• target/espressif: Added GDB File I/O support (https://sourceware.org/gdb/onlinedocs/gdb/File_002dI_002fO-Overview.html).
• target/espressif: Added support for stack hardware protection in RISC-V chips.
• helper/log: Added log_non_error_levels_to_stdout command to send non-error logs to stdout. This can be useful for IDEs to detect errors messages.
• jtag/drivers: Added SWD bitbang support for esp_gpio driver.
• loaders/esp32{c2,h2,c6}: Added cpu_clock_configure functionality. This allows to improve flash access speed by temporary boosting CPU clock by flasher stub.
• loaders/esp32{h2,c6}: Added flash encryption support.

Bug fixes:

• target/xtensa: Fixed GDB watchpoint hit location handling to show previous and new value. Previously watchpoint hit just before memory access and no stepping over store/load instruction was performed, so GDB did not showed old and new variable value.
• target/esp32s3: Keep APP_CPU clock gating enabled after SW reset. It avoids extra core 1 reset by IDF code which can lead to loosing breakpoints set on that core.
• target/espressif: Suppressed empty Gcov file read error. During Gcov data dump, target code tries to read existing but empty Gcov data file. So for the first dump it generates error message what actually does not indicate an error.
• target/esp_common: Fixed handling of spaces in file paths ensuring that command arguments are handled properly.

Other:

• target/espressif: DRAM used as the single work area
• tcl/espressif: Removed alt-workarea-xxx commands.
• jtag/drivers: SWD bitbang changed to use dedicated gpio for esp_gpio driver. It sould improve latency and speed of communication (https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/peripherals/dedic_gpio.html).
• jtag/drivers: Renamed esp32gpio driver to esp_gpio.
• target/espressif: Removed deprecated semihost_basedir command.
• tcl/esp32: Removed deprecated program_esp32 function.
• Synced with upstream at openocd-org/openocd@3b78b5c

v0.12.0-esp32-20230419

Features:

• target/xtensa: Added NX processors support

Bug fixes:

• esp: libjaylink and hidapi support added into the release binaries. This will allow users to debug with Segger Jlink and CMSIS-DAP compatible adapters.
• target/xtensa: Implemented hit_watchpoint callback. It made watchpoint behavior on Xtensa similar to other architectures (e.g. RISCV and ARM). Previously target was stopped just before the data are changed. Now it is stopped just after the data are changed in memory.

v0.12.0-esp32-20230313

Features:

• target/esp: Adds check for openocd binary and .cfg file versions match. Error message is printed when user try to run openocd with configured TCL scripts directory from another OpenOCD release. See #276 (comment).
• jtag/esp_usb_jtag: Try to reset usb device on read errors. Try to reset USB JTAG device on read errors as it is done for write errors.

Bug fixes:

• esp/apptrace: Fixes 'esp sysview stop' return code. After recent changes that command always returned error.
• target/esp32h2: Fixes reset reason value.
• target/esp_riscv: Clears apptrace ctrl block address on target reset. That prevents using old apptrace ctrl block address when application image is updated w/o OpenOCD restart.

v0.12.0-esp32-20230221

Features:

• target: Added base support for ESP32-C6.
• target: Added base support for ESP32-H2.
• flash/esp: Added support for the detection of 32-256MB flash chips. See #245.
• flash/esp: Added possibility to control if binary needs to be written encrypted or not. Added encrypt option to program_esp command. program_esp_bins decides if the partition is encrypted or not based on flash_args.json. Previously the decision was based on the fuses' configuration only. Solves the problem described here.
• flash/esp: Added esp stub_log <on|off> command. This command controls if flasher stub log messages should be read and printed along with OpenOCD ones. It should be very useful for user issues diagnostics.
• driver/usb: Updated libusb to 1.0.26 in MacOS and Windows builts. It eliminates LIBUSB_ERROR_NOT_SUPPORTED error reported on Windows which actually did not break anything. See #255.
• flash/esp: Added extra warning messages for some flasher stub return codes. They are intended to avoid users' confusion described in #260 (comment)

Bug Fixes:

• flash/esp: Fixes PSRAM corruption by flasher stub on ESP32-S2/S3. Solves #264.
• rtos/FreeRTOS: decrease log level of uxTopUsedPriority read issue. This error is also reported when the chip is just reset and the app data segment is not mapped yet by the bootloader. To avoid user's confusion its log level was changed.
• target/xtensa: change the log level of Unexpected OCD_ID error. This error is also reported when single-core app is running on a multi-core chip (only one core is enabled). To avoid user confusion its log level was changed.
• target/esp_riscv: Corrects maximum breakpoints and watchpoints numbers per target for different chips

Other:

• openocd: Added cmake build support.
• jtag/drivers: esp32 gpio bitbang changed to use dedicated gpio driver. This should improve the performance of the esp32gpio bitbang driver.
• Synced with upstream at https://github.com/openocd-org/openocd/commits/master/85ae73de03ebcc723842b7978a6c94b73166f027.loaders/esp: convert return codes to warning messages

v0.11.0-esp32-20221026

Features:

• esp: Adds reset cause printing. Now message with reset cause for every core of the chip is printed in a numerical and human-readable format.
• esp/xtensa: Adds exception cause printing. Now message with the exception cause for Xtensa chips is printed in a numerical and human-readable format.
• esp32c2: Adds flash encryption support.
• rtos/nuttx: Adds ESP32-C3 support.
• rtos/nuttx: Adds ESP32-S2 support.
• rtos/nuttx: Adds ESP32-S3 support.
• Releases binaries with remote bitbang support enabled.

Bug fixes:

• Workarounds problem reported again in espressif/esp-idf#8065 (comment) by retrying memory read on failure. That problem led to "Step into" instead of "Step over" and other weird stuff like seemingly corrupting the stack during debugging.
• esp/xtensa: Allows reading internal ROM by default. This bug led to memory read errors when GDB tried to unwind backtraces containing ROM functions.
• esp/xtensa: Fixes data corruption on the first variable read. In some cases, this bug led to the reading of garbage data from memory.
• esp_usb_jtag: Sanity check to prevent possible buffer overflow at the output buffer
• esp/riscv: Filters out target halts caused normal debugging activities. This bug led to the message with exception reason printed on any target halt including those caused by normal debugging activities: breakpoints, stepping, manual program interruption by the user, etc.
• esp/riscv: Fixes watchpoints reconfiguration from target. This bug led to "HW watchpoints slots leaks" when the target program set/re-configured the watchpoint with the same ID several times.

Other:

• esp/xtensa: Rebased code base onto upstream Cadence generic Xtensa target implementation.
• Synchronized with upstream changes.
• Refactored for upstreaming patches.

v0.11.0-esp32-20220706

2022/07/06 Release, based on OpenOCD v0.11.0

Features:

• esp32c2: Adds generic support for ESP32-C2.
• esp32c3: Implements logging the reason of the reset. The reason is printed in numerical and human readable format.
• espxx: Implements soft_reset_halt command.
• esp/semihosting: Adds full support for ESP IDF VFS driver directory API.
• esp/flash: Adds no_clock_boost argument to program_esp and program_esp_bins commands. This can be helpful when users experience problems with flash programming. It forbids OpenOCD to modify (boost) CPU clock in order to speed up flashing.
• freertos: Adds support for qGetTLSAddr GDB packet. This fixes problem appeared on Xtensa targets when user tried to print TLS variable value in GDB.
• freertos: Enables reading some Xtensa registers for waiting tasks (e.g. threadptr). Zero values were returned before this change.
• freertos: Support Amazon FreeRTOS SMP port (available in IDF starting from IDF 5.0)
• doc: Updates description of Espressif-specific commands.

Bug fixes:

• esp32s3: call smp_target_init instead of single core init.
• rtos/esp32: Fixed AddressSanitizer heap-buffer-overflow issue when reading registers from ESP32 stack.
• xtensa: Invalidates register cache on reset. This could lead to writing to target old registers values after chip reset and could lead to unpredictable behavior.
• esp/flash: Fixed memory leaks in ESP flash driver reported by valgrind.

Other:

• Synchronized with upstream changes
• Refactored for upstreaming patches