Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED and Error: Failed to get flash maps (4294967290)! (OCD-666)

[skanky-dev]

Development Kit

Custom Hardware

Module or chip used

ESP32-WROOM-32E (16MB)

Debug Adapter

ESP-PROG

OpenOCD version

v0.11.0-esp32-20220706

Operating System

Win10 Pro

Using an IDE ?

Command line and VS Code

OpenOCD command line

C:\Espressif\frameworks\esp-idf-v4.4.3>openocd -f board/esp32-wrover-kit-3.3v.cfg

JTAG Clock Speed

20000 kHz

ESP-IDF version

1.0.3

Problem Description

Using this on the command line: openocd -l openocd_log.txt -f board/esp32-wrover-kit-3.3v.cfg -c "init; reset halt; flash erase_address 0x1000 61440; exit"

I get errors and warnings that I can find no explanation or resolution for:
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Error: Failed to get flash maps (4294967290)!
Warn : Failed to get flash mappings (-4)!

Debug Logs

Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 20000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : [esp32.cpu0] Target halted, PC=0x40000400, debug_reason=00000001
Info : [esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
Info : starting gdb server for esp32.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : [esp32.cpu0] requesting target halt and executing a soft reset
Info : [esp32.cpu0] Debug controller was reset.
Info : [esp32.cpu0] Core was reset.
Info : [esp32.cpu0] Target halted, PC=0x500000CF, debug_reason=00000000
Info : Set GDB target to 'esp32.cpu0'
Info : [esp32.cpu1] requesting target halt and executing a soft reset
Info : [esp32.cpu0] Core was reset.
Info : [esp32.cpu0] Target halted, PC=0x40000400, debug_reason=00000000
Info : [esp32.cpu1] Debug controller was reset.
Info : [esp32.cpu1] Core was reset.
Info : [esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
Info : [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Error: Failed to get flash maps (4294967290)!
Warn : Failed to get flash mappings (-4)!
Info : [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Info : [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Info : Auto-detected flash bank 'esp32.cpu1.flash' size 4096 KB
Info : Using flash bank 'esp32.cpu1.flash' size 4096 KB
Info : [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Info : PROF: Erased 61440 bytes in 657.367 ms

Expected behavior

Operation should complete without errors

Screenshots

[skanky-dev]

Here it is with -d3 output:

User : 3 0 options.c:63 configuration_output_handler(): debug_level: 3
User : 4 0 options.c:63 configuration_output_handler():
Debug: 5 0 options.c:244 add_default_dirs(): bindir=/builds/idf/openocd-esp32/_build/../openocd-esp32/bin
Debug: 6 0 options.c:245 add_default_dirs(): pkgdatadir=/builds/idf/openocd-esp32/_build/../openocd-esp32/share/openocd
Debug: 7 0 options.c:246 add_default_dirs(): exepath=C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin
Debug: 8 0 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 9 0 configuration.c:44 add_script_search_dir(): adding C:/Users/Dev/AppData/Roaming/OpenOCD
Debug: 10 0 configuration.c:44 add_script_search_dir(): adding C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/site
Debug: 11 0 configuration.c:44 add_script_search_dir(): adding C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/scripts
Debug: 12 0 command.c:166 script_debug(): command - ocd_find board/esp32-wrover-kit-3.3v.cfg
Debug: 13 0 configuration.c:99 find_file(): found C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/scripts/board/esp32-wrover-kit-3.3v.cfg
Debug: 14 0 command.c:166 script_debug(): command - ocd_find interface/ftdi/esp32_devkitj_v1.cfg
Debug: 15 0 configuration.c:99 find_file(): found C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/scripts/interface/ftdi/esp32_devkitj_v1.cfg
Debug: 16 0 command.c:166 script_debug(): command - adapter driver ftdi
Debug: 17 0 command.c:166 script_debug(): command - ftdi vid_pid 0x0403 0x6010 0x0403 0x6014
Debug: 18 0 command.c:166 script_debug(): command - ftdi channel 0
Debug: 19 0 command.c:166 script_debug(): command - ftdi layout_init 0x0008 0xf00b
Debug: 20 0 command.c:166 script_debug(): command - ftdi layout_signal LED -data 0x1000
Debug: 21 0 command.c:166 script_debug(): command - ftdi layout_signal LED2 -data 0x2000
Debug: 22 0 command.c:166 script_debug(): command - ftdi layout_signal LED3 -data 0x4000
Debug: 23 0 command.c:166 script_debug(): command - ftdi layout_signal LED4 -data 0x8000
Debug: 24 0 command.c:166 script_debug(): command - adapter speed 20000
Debug: 25 0 adapter.c:180 adapter_config_khz(): handle adapter khz
Debug: 26 0 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 27 0 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 28 0 command.c:166 script_debug(): command - ocd_find target/esp32.cfg
Debug: 29 0 configuration.c:99 find_file(): found C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/scripts/target/esp32.cfg
Debug: 30 0 command.c:166 script_debug(): command - transport select jtag
Debug: 31 0 command.c:166 script_debug(): command - ocd_find target/esp_common.cfg
Debug: 32 0 configuration.c:99 find_file(): found C:/Users/Dev/.espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/scripts/target/esp_common.cfg
Debug: 33 0 command.c:166 script_debug(): command - add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock are optional
Debug: 34 0 command.c:166 script_debug(): command - add_usage_text program_esp [address] [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock]
Debug: 35 0 command.c:166 script_debug(): command - add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project
Debug: 36 0 command.c:166 script_debug(): command - add_usage_text program_esp_bins <build_dir> flasher_args.json [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock]
Debug: 37 0 command.c:166 script_debug(): command - add_help_text esp_get_mac Print MAC address of the chip. Use a format argument to return formatted MAC value
Debug: 38 0 command.c:166 script_debug(): command - add_usage_text esp_get_mac [format]
Debug: 39 0 command.c:166 script_debug(): command - jtag newtap esp32 cpu0 -irlen 5 -expected-id 0x120034e5
Debug: 40 0 tcl.c:569 jim_newtap_cmd(): Creating New Tap, Chip: esp32, Tap: cpu0, Dotted: esp32.cpu0, 4 params
Debug: 41 0 tcl.c:593 jim_newtap_cmd(): Processing option: -irlen
Debug: 42 0 tcl.c:593 jim_newtap_cmd(): Processing option: -expected-id
Debug: 43 0 core.c:1472 jtag_tap_init(): Created Tap: esp32.cpu0 @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 44 0 command.c:166 script_debug(): command - jtag newtap esp32 cpu1 -irlen 5 -expected-id 0x120034e5
Debug: 45 0 tcl.c:569 jim_newtap_cmd(): Creating New Tap, Chip: esp32, Tap: cpu1, Dotted: esp32.cpu1, 4 params
Debug: 46 0 tcl.c:593 jim_newtap_cmd(): Processing option: -irlen
Debug: 47 0 tcl.c:593 jim_newtap_cmd(): Processing option: -expected-id
Debug: 48 0 core.c:1472 jtag_tap_init(): Created Tap: esp32.cpu1 @ abs position 1, irlen 5, capture: 0x1 mask: 0x3
Debug: 49 0 command.c:166 script_debug(): command - target create esp32.cpu0 esp32 -endian little -chain-position esp32.cpu0 -coreid 0 -rtos FreeRTOS
Debug: 50 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 51 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 52 0 FreeRTOS.c:1387 freertos_create(): freertos_create
Debug: 53 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 54 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 55 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 56 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 57 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 58 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 59 0 command.c:300 register_command(): command 'esp32 flashbootstrap' is already registered
Debug: 60 0 command.c:300 register_command(): command 'esp32.cpu0 esp' is already registered
Debug: 61 0 command.c:300 register_command(): command 'esp32.cpu0 esp32' is already registered
Debug: 62 0 command.c:300 register_command(): command 'esp32.cpu0 esp32' is already registered
Debug: 63 0 command.c:300 register_command(): command 'esp32.cpu0 esp32' is already registered
Debug: 64 0 command.c:300 register_command(): command 'esp32.cpu0 esp32' is already registered
Debug: 65 0 command.c:300 register_command(): command 'esp32.cpu0 esp32' is already registered
Debug: 66 0 command.c:300 register_command(): command 'esp32.cpu0 esp32 flashbootstrap' is already registered
Debug: 67 0 command.c:166 script_debug(): command - esp32.cpu0 configure -work-area-phys 0x40090000 -work-area-virt 0x40090000 -work-area-size 0x4000 -work-area-backup 1
Debug: 68 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 69 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 70 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 71 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 72 0 command.c:166 script_debug(): command - esp32.cpu0 configure -alt-work-area-phys 0x3FFC0000 -alt-work-area-virt 0x3FFC0000 -alt-work-area-size 0x18000 -alt-work-area-backup 1
Debug: 73 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 74 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 75 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 76 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 77 0 command.c:166 script_debug(): command - flash bank esp32.cpu0.flash esp32 0x0 0 0 0 esp32.cpu0
Debug: 78 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 79 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 80 0 tcl.c:1316 handle_flash_bank_command(): 'esp32' driver usage field missing
Debug: 81 0 command.c:166 script_debug(): command - flash bank esp32.cpu0.irom esp32 0x0 0 0 0 esp32.cpu0
Debug: 82 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 83 0 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 84 0 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 85 0 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 86 0 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 87 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 88 0 command.c:300 register_command(): command 'esp32 appimage_offset' is already registered
Debug: 89 0 command.c:300 register_command(): command 'esp32 compression' is already registered
Debug: 90 0 command.c:300 register_command(): command 'esp32 verify_bank_hash' is already registered
Debug: 91 0 command.c:300 register_command(): command 'esp32 flash_stub_clock_boost' is already registered
Debug: 92 0 tcl.c:1316 handle_flash_bank_command(): 'esp32' driver usage field missing
Debug: 93 0 command.c:166 script_debug(): command - flash bank esp32.cpu0.drom esp32 0x0 0 0 0 esp32.cpu0
Debug: 94 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 95 0 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 96 0 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 97 0 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 98 0 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 99 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 100 0 command.c:300 register_command(): command 'esp32 appimage_offset' is already registered
Debug: 101 0 command.c:300 register_command(): command 'esp32 compression' is already registered
Debug: 102 0 command.c:300 register_command(): command 'esp32 verify_bank_hash' is already registered
Debug: 103 0 command.c:300 register_command(): command 'esp32 flash_stub_clock_boost' is already registered
Debug: 104 0 tcl.c:1316 handle_flash_bank_command(): 'esp32' driver usage field missing
Debug: 105 0 command.c:166 script_debug(): command - target create esp32.cpu1 esp32 -endian little -chain-position esp32.cpu1 -coreid 1 -rtos FreeRTOS
Debug: 106 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 107 0 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 108 0 FreeRTOS.c:1387 freertos_create(): freertos_create
Debug: 109 0 command.c:300 register_command(): command 'xtensa' is already registered
Debug: 110 0 command.c:300 register_command(): command 'xtensa set_permissive' is already registered
Debug: 111 0 command.c:300 register_command(): command 'xtensa maskisr' is already registered
Debug: 112 0 command.c:300 register_command(): command 'xtensa smpbreak' is already registered
Debug: 113 0 command.c:300 register_command(): command 'xtensa perfmon_enable' is already registered
Debug: 114 0 command.c:300 register_command(): command 'xtensa perfmon_dump' is already registered
Debug: 115 0 command.c:300 register_command(): command 'xtensa tracestart' is already registered
Debug: 116 0 command.c:300 register_command(): command 'xtensa tracestop' is already registered
Debug: 117 0 command.c:300 register_command(): command 'xtensa tracedump' is already registered
Debug: 118 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 119 0 command.c:300 register_command(): command 'esp semihost_basedir' is already registered
Debug: 120 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 121 0 command.c:300 register_command(): command 'esp apptrace' is already registered
Debug: 122 0 command.c:300 register_command(): command 'esp sysview' is already registered
Debug: 123 0 command.c:300 register_command(): command 'esp sysview_mcore' is already registered
Debug: 124 0 command.c:300 register_command(): command 'esp gcov' is already registered
Debug: 125 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 126 0 command.c:300 register_command(): command 'esp32 smp' is already registered
Debug: 127 0 command.c:300 register_command(): command 'esp32 smp_gdb' is already registered
Debug: 128 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 129 0 command.c:300 register_command(): command 'esp32 flashbootstrap' is already registered
Debug: 130 0 command.c:300 register_command(): command 'arm' is already registered
Debug: 131 0 command.c:300 register_command(): command 'arm semihosting' is already registered
Debug: 132 0 command.c:300 register_command(): command 'arm semihosting_redirect' is already registered
Debug: 133 0 command.c:300 register_command(): command 'arm semihosting_cmdline' is already registered
Debug: 134 0 command.c:300 register_command(): command 'arm semihosting_fileio' is already registered
Debug: 135 0 command.c:300 register_command(): command 'arm semihosting_resexit' is already registered
Debug: 136 0 command.c:300 register_command(): command 'arm semihosting_read_user_param' is already registered
Debug: 137 0 command.c:300 register_command(): command 'arm semihosting_basedir' is already registered
Debug: 138 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 139 0 command.c:300 register_command(): command 'esp32 set_permissive' is already registered
Debug: 140 0 command.c:300 register_command(): command 'esp32 maskisr' is already registered
Debug: 141 0 command.c:300 register_command(): command 'esp32 smpbreak' is already registered
Debug: 142 0 command.c:300 register_command(): command 'esp32 perfmon_enable' is already registered
Debug: 143 0 command.c:300 register_command(): command 'esp32 perfmon_dump' is already registered
Debug: 144 0 command.c:300 register_command(): command 'esp32 tracestart' is already registered
Debug: 145 0 command.c:300 register_command(): command 'esp32 tracestop' is already registered
Debug: 146 0 command.c:300 register_command(): command 'esp32 tracedump' is already registered
Debug: 147 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 148 0 command.c:300 register_command(): command 'esp32 semihost_basedir' is already registered
Debug: 149 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 150 0 command.c:300 register_command(): command 'esp32 apptrace' is already registered
Debug: 151 0 command.c:300 register_command(): command 'esp32 sysview' is already registered
Debug: 152 0 command.c:300 register_command(): command 'esp32 sysview_mcore' is already registered
Debug: 153 0 command.c:300 register_command(): command 'esp32 gcov' is already registered
Debug: 154 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 155 0 command.c:300 register_command(): command 'esp32 flashbootstrap' is already registered
Debug: 156 0 command.c:300 register_command(): command 'esp32.cpu1 esp' is already registered
Debug: 157 0 command.c:300 register_command(): command 'esp32.cpu1 esp32' is already registered
Debug: 158 0 command.c:300 register_command(): command 'esp32.cpu1 esp32' is already registered
Debug: 159 0 command.c:300 register_command(): command 'esp32.cpu1 esp32' is already registered
Debug: 160 0 command.c:300 register_command(): command 'esp32.cpu1 esp32' is already registered
Debug: 161 0 command.c:300 register_command(): command 'esp32.cpu1 esp32' is already registered
Debug: 162 0 command.c:300 register_command(): command 'esp32.cpu1 esp32 flashbootstrap' is already registered
Debug: 163 0 command.c:166 script_debug(): command - flash bank esp32.cpu1.flash esp32 0x0 0 0 0 esp32.cpu1
Debug: 164 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 165 0 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 166 0 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 167 0 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 168 0 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 169 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 170 0 command.c:300 register_command(): command 'esp32 appimage_offset' is already registered
Debug: 171 0 command.c:300 register_command(): command 'esp32 compression' is already registered
Debug: 172 0 command.c:300 register_command(): command 'esp32 verify_bank_hash' is already registered
Debug: 173 0 command.c:300 register_command(): command 'esp32 flash_stub_clock_boost' is already registered
Debug: 174 0 tcl.c:1316 handle_flash_bank_command(): 'esp32' driver usage field missing
Debug: 175 0 command.c:166 script_debug(): command - flash bank esp32.cpu1.irom esp32 0x0 0 0 0 esp32.cpu1
Debug: 176 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 177 0 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 178 0 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 179 0 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 180 0 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 181 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 182 0 command.c:300 register_command(): command 'esp32 appimage_offset' is already registered
Debug: 183 0 command.c:300 register_command(): command 'esp32 compression' is already registered
Debug: 184 0 command.c:300 register_command(): command 'esp32 verify_bank_hash' is already registered
Debug: 185 0 command.c:300 register_command(): command 'esp32 flash_stub_clock_boost' is already registered
Debug: 186 0 tcl.c:1316 handle_flash_bank_command(): 'esp32' driver usage field missing
Debug: 187 0 command.c:166 script_debug(): command - flash bank esp32.cpu1.drom esp32 0x0 0 0 0 esp32.cpu1
Debug: 188 0 command.c:300 register_command(): command 'esp' is already registered
Debug: 189 0 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 190 0 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 191 0 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 192 0 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 193 0 command.c:300 register_command(): command 'esp32' is already registered
Debug: 194 0 command.c:300 register_command(): command 'esp32 appimage_offset' is already registered
Debug: 195 0 command.c:300 register_command(): command 'esp32 compression' is already registered
Debug: 196 0 command.c:300 register_command(): command 'esp32 verify_bank_hash' is already registered
Debug: 197 0 command.c:300 register_command(): command 'esp32 flash_stub_clock_boost' is already registered
Debug: 198 0 tcl.c:1316 handle_flash_bank_command(): 'esp32' driver usage field missing
Debug: 199 0 command.c:166 script_debug(): command - target smp esp32.cpu0 esp32.cpu1
Debug: 200 0 target.c:6562 jim_target_smp(): 3
Debug: 201 0 target.c:6579 jim_target_smp(): esp32.cpu0
Debug: 202 0 target.c:6579 jim_target_smp(): esp32.cpu1
Debug: 203 0 command.c:166 script_debug(): command - esp32.cpu0 esp32 flashbootstrap 3.3
Debug: 204 0 command.c:166 script_debug(): command - esp32.cpu0 xtensa maskisr on
Debug: 205 0 command.c:166 script_debug(): command - esp32.cpu0 xtensa smpbreak BreakIn BreakOut
Debug: 206 0 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=30000, state=1
Debug: 207 0 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu1] set smpbreak=30000, state=1
Debug: 208 0 command.c:166 script_debug(): command - esp32.cpu0 configure -event reset-assert-post soft_reset_halt
Debug: 209 0 command.c:166 script_debug(): command - esp32.cpu0 configure -event gdb-attach
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
# necessary to auto-probe flash bank when GDB is connected
halt 1000

Debug: 210 0 command.c:166 script_debug(): command - esp32.cpu1 configure -event gdb-attach
$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
# necessary to auto-probe flash bank when GDB is connected
halt 1000

Debug: 211 0 command.c:166 script_debug(): command - esp32.cpu1 configure -event reset-assert-post soft_reset_halt
Debug: 212 0 command.c:166 script_debug(): command - esp32.cpu0 configure -event examine-end
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 213 0 command.c:166 script_debug(): command - esp32.cpu1 configure -event examine-end
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 214 0 command.c:166 script_debug(): command - add_help_text program_esp32 write an image to flash, address is only required for binary images. verify, reset, exit are optional
Debug: 215 0 command.c:166 script_debug(): command - add_usage_text program_esp32 [address] [verify] [reset] [exit]
Debug: 216 0 command.c:166 script_debug(): command - init
Debug: 217 0 command.c:166 script_debug(): command - target init
Debug: 218 0 command.c:166 script_debug(): command - target names
Debug: 219 0 command.c:166 script_debug(): command - esp32.cpu0 cget -event gdb-flash-erase-start
Debug: 220 0 command.c:166 script_debug(): command - esp32.cpu0 configure -event gdb-flash-erase-start reset init
Debug: 221 0 command.c:166 script_debug(): command - esp32.cpu0 cget -event gdb-flash-write-end
Debug: 222 0 command.c:166 script_debug(): command - esp32.cpu0 configure -event gdb-flash-write-end reset halt
Debug: 223 0 command.c:166 script_debug(): command - esp32.cpu0 cget -event gdb-attach
Debug: 224 0 command.c:166 script_debug(): command - esp32.cpu1 cget -event gdb-flash-erase-start
Debug: 225 0 command.c:166 script_debug(): command - esp32.cpu1 configure -event gdb-flash-erase-start reset init
Debug: 226 0 command.c:166 script_debug(): command - esp32.cpu1 cget -event gdb-flash-write-end
Debug: 227 0 command.c:166 script_debug(): command - esp32.cpu1 configure -event gdb-flash-write-end reset halt
Debug: 228 0 command.c:166 script_debug(): command - esp32.cpu1 cget -event gdb-attach
Debug: 229 0 target.c:1672 handle_target_init_command(): Initializing targets...
Debug: 230 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'litbase' (152) does not exist
Debug: 231 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'ptevaddr' (153) does not exist
Debug: 232 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'rasid' (154) does not exist
Debug: 233 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'itlbcfg' (155) does not exist
Debug: 234 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'dtlbcfg' (156) does not exist
Debug: 235 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mepc' (157) does not exist
Debug: 236 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'meps' (158) does not exist
Debug: 237 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mesave' (159) does not exist
Debug: 238 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mesr' (160) does not exist
Debug: 239 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mecr' (161) does not exist
Debug: 240 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mevaddr' (162) does not exist
Debug: 241 0 semihosting_common.c:118 semihosting_common_init():
Debug: 242 0 semihosting_common.c:118 semihosting_common_init():
Debug: 243 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'litbase' (152) does not exist
Debug: 244 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'ptevaddr' (153) does not exist
Debug: 245 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'rasid' (154) does not exist
Debug: 246 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'itlbcfg' (155) does not exist
Debug: 247 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'dtlbcfg' (156) does not exist
Debug: 248 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mepc' (157) does not exist
Debug: 249 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'meps' (158) does not exist
Debug: 250 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mesave' (159) does not exist
Debug: 251 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mesr' (160) does not exist
Debug: 252 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mecr' (161) does not exist
Debug: 253 0 xtensa.c:2292 xtensa_build_reg_cache(): Special reg 'mevaddr' (162) does not exist
Debug: 254 0 semihosting_common.c:118 semihosting_common_init():
Debug: 255 0 semihosting_common.c:118 semihosting_common_init():
Debug: 256 0 ftdi.c:665 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Error: 257 34 mpsse.c:191 open_matching_device(): libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Debug: 258 34 mpsse.c:423 mpsse_purge(): -
Debug: 259 47 mpsse.c:704 mpsse_loopback_config(): off
Debug: 260 47 mpsse.c:749 mpsse_set_frequency(): target 20000000 Hz
Debug: 261 47 mpsse.c:741 mpsse_rtck_config(): off
Debug: 262 47 mpsse.c:730 mpsse_divide_by_5_config(): off
Debug: 263 47 mpsse.c:710 mpsse_set_divisor(): 1
Debug: 264 47 mpsse.c:773 mpsse_set_frequency(): actually 15000000 Hz
Debug: 265 47 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 266 47 adapter.c:148 adapter_khz_to_speed(): have adapter set up
Debug: 267 47 mpsse.c:749 mpsse_set_frequency(): target 20000000 Hz
Debug: 268 47 mpsse.c:741 mpsse_rtck_config(): off
Debug: 269 47 mpsse.c:730 mpsse_divide_by_5_config(): off
Debug: 270 47 mpsse.c:710 mpsse_set_divisor(): 1
Debug: 271 47 mpsse.c:773 mpsse_set_frequency(): actually 15000000 Hz
Info : 272 47 ftdi.c:291 ftdi_speed(): ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Debug: 273 47 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 274 47 adapter.c:148 adapter_khz_to_speed(): have adapter set up
Info : 275 47 adapter.c:108 adapter_init(): clock speed 20000 kHz
Debug: 276 47 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 277 47 command.c:166 script_debug(): command - transport init
Debug: 278 47 transport.c:230 handle_transport_init(): handle_transport_init
Debug: 279 47 core.c:824 jtag_add_reset(): SRST line released
Debug: 280 47 core.c:849 jtag_add_reset(): TRST line released
Debug: 281 47 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 282 47 command.c:166 script_debug(): command - jtag arp_init
Debug: 283 47 core.c:1503 jtag_init_inner(): Init JTAG chain
Debug: 284 47 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 285 47 core.c:1228 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 286 47 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 287 47 core.c:1127 jtag_examine_chain_display(): JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : 288 47 core.c:1127 jtag_examine_chain_display(): JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Debug: 289 47 core.c:1358 jtag_validate_ircapture(): IR capture validation scan
Debug: 290 47 core.c:1416 jtag_validate_ircapture(): esp32.cpu0: IR capture 0x01
Debug: 291 47 core.c:1416 jtag_validate_ircapture(): esp32.cpu1: IR capture 0x01
Debug: 292 47 command.c:166 script_debug(): command - dap init
Debug: 293 47 arm_dap.c:109 dap_init_all(): Initializing all DAPs ...
Debug: 294 47 openocd.c:160 handle_init_command(): Examining targets...
Debug: 295 47 target.c:1860 target_call_event_callbacks(): target event 19 (examine-start) for core esp32.cpu0
Debug: 296 47 esp32.c:508 esp32_handle_target_event(): 19
Debug: 297 47 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 19
Debug: 298 47 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 19
Debug: 299 47 xtensa.c:2392 xtensa_handle_target_event(): 19
Debug: 300 47 xtensa.c:737 xtensa_examine(): coreid = 0
Debug: 301 47 xtensa.c:749 xtensa_examine(): OCD_ID = 0733bff2
Debug: 302 47 target.c:1860 target_call_event_callbacks(): target event 21 (examine-end) for core esp32.cpu0
Debug: 303 47 target.c:5153 target_handle_event(): target(0): esp32.cpu0 (esp32) event: 21 (examine-end) action:
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 304 47 command.c:166 script_debug(): command - arm semihosting enable
Debug: 305 47 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 306 47 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 307 47 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 308 47 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 309 47 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x40000400, debug_reason=00000001, oldstate=00000001
Debug: 310 47 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000008, exc_cause=0, dsr=0x8080cc11
Info : 311 47 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x40000400, debug_reason=00000001
Debug: 312 47 esp_xtensa_smp.c:176 esp_xtensa_smp_poll(): [esp32.cpu0] Check for unexamined cores after reset
Debug: 313 47 target.c:1860 target_call_event_callbacks(): target event 19 (examine-start) for core esp32.cpu1
Debug: 314 47 esp32.c:508 esp32_handle_target_event(): 19
Debug: 315 47 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 19
Debug: 316 47 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 19
Debug: 317 47 xtensa.c:2392 xtensa_handle_target_event(): 19
Debug: 318 47 xtensa.c:737 xtensa_examine(): coreid = 1
Debug: 319 58 xtensa.c:749 xtensa_examine(): OCD_ID = 0733bff2
Debug: 320 58 target.c:1860 target_call_event_callbacks(): target event 21 (examine-end) for core esp32.cpu1
Debug: 321 58 target.c:5153 target_handle_event(): target(1): esp32.cpu1 (esp32) event: 21 (examine-end) action:
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 322 58 command.c:166 script_debug(): command - arm semihosting enable
Debug: 323 58 esp_xtensa_semihosting.c:49 esp_xtensa_semihosting_setup(): [esp32.cpu1] semihosting enable=1
Debug: 324 58 command.c:166 script_debug(): command - arm semihosting_resexit enable
Debug: 325 58 command.c:166 script_debug(): command - arm semihosting_basedir .
Debug: 326 58 esp32.c:508 esp32_handle_target_event(): 21
Debug: 327 58 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 21
Debug: 328 58 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 21
Debug: 329 58 xtensa.c:2392 xtensa_handle_target_event(): 21
Debug: 330 58 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu1] write smpbreak set=0x30000 clear=0x600000
Debug: 331 58 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 332 58 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 333 58 esp_xtensa_smp.c:286 esp_xtensa_smp_update_halt_gdb(): Poll target 'esp32.cpu1'
Debug: 334 58 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu1] start
Debug: 335 58 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 336 58 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 337 58 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 338 58 xtensa.c:1808 xtensa_poll(): [esp32.cpu1] Target halted, pc=0x40000400, debug_reason=00000000, oldstate=00000001
Debug: 339 58 xtensa.c:1812 xtensa_poll(): [esp32.cpu1] Halt reason=0x00000020, exc_cause=0, dsr=0x8080cc11
Info : 340 58 xtensa.c:1814 xtensa_poll(): [esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
Debug: 341 58 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32.cpu1
Debug: 342 58 esp32.c:508 esp32_handle_target_event(): 0
Debug: 343 58 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 0
Debug: 344 58 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 0
Debug: 345 58 xtensa.c:2392 xtensa_handle_target_event(): 0
Debug: 346 58 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32.cpu1
Debug: 347 58 esp32.c:508 esp32_handle_target_event(): 1
Debug: 348 58 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 1
Debug: 349 58 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 1
Debug: 350 58 xtensa.c:2392 xtensa_handle_target_event(): 1
Debug: 351 58 target.c:2778 target_write_u32(): address: 0x3ff5f064, value: 0x50d83aa1
Debug: 352 58 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 353 58 target.c:2778 target_write_u32(): address: 0x3ff5f048, value: 0x00000000
Debug: 354 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 355 68 target.c:2778 target_write_u32(): address: 0x3ff60064, value: 0x50d83aa1
Debug: 356 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 357 68 target.c:2778 target_write_u32(): address: 0x3ff60048, value: 0x00000000
Debug: 358 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 359 68 target.c:2778 target_write_u32(): address: 0x3ff480a4, value: 0x50d83aa1
Debug: 360 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 361 68 target.c:2778 target_write_u32(): address: 0x3ff4808c, value: 0x00000000
Debug: 362 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 363 68 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 364 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 365 68 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32.cpu0
Debug: 366 68 esp32.c:508 esp32_handle_target_event(): 0
Debug: 367 68 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 0
Debug: 368 68 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 0
Debug: 369 68 xtensa.c:2392 xtensa_handle_target_event(): 0
Debug: 370 68 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32.cpu0
Debug: 371 68 esp32.c:508 esp32_handle_target_event(): 1
Debug: 372 68 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 1
Debug: 373 68 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 1
Debug: 374 68 xtensa.c:2392 xtensa_handle_target_event(): 1
Debug: 375 68 target.c:2778 target_write_u32(): address: 0x3ff5f064, value: 0x50d83aa1
Debug: 376 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 377 68 target.c:2778 target_write_u32(): address: 0x3ff5f048, value: 0x00000000
Debug: 378 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 379 68 target.c:2778 target_write_u32(): address: 0x3ff60064, value: 0x50d83aa1
Debug: 380 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 381 68 target.c:2778 target_write_u32(): address: 0x3ff60048, value: 0x00000000
Debug: 382 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 383 68 target.c:2778 target_write_u32(): address: 0x3ff480a4, value: 0x50d83aa1
Debug: 384 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 385 68 target.c:2778 target_write_u32(): address: 0x3ff4808c, value: 0x00000000
Debug: 386 68 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 387 68 esp_xtensa_smp.c:176 esp_xtensa_smp_poll(): [esp32.cpu1] Check for unexamined cores after reset
Debug: 388 68 esp_xtensa_semihosting.c:49 esp_xtensa_semihosting_setup(): [esp32.cpu0] semihosting enable=1
Debug: 389 68 command.c:166 script_debug(): command - arm semihosting_resexit enable
Debug: 390 68 command.c:166 script_debug(): command - arm semihosting_basedir .
Debug: 391 68 esp32.c:508 esp32_handle_target_event(): 21
Debug: 392 68 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 21
Debug: 393 68 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 21
Debug: 394 68 xtensa.c:2392 xtensa_handle_target_event(): 21
Debug: 395 68 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x30000 clear=0x600000
Debug: 396 68 target.c:1860 target_call_event_callbacks(): target event 19 (examine-start) for core esp32.cpu1
Debug: 397 68 esp32.c:508 esp32_handle_target_event(): 19
Debug: 398 68 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 19
Debug: 399 68 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 19
Debug: 400 68 xtensa.c:2392 xtensa_handle_target_event(): 19
Debug: 401 68 xtensa.c:737 xtensa_examine(): coreid = 1
Debug: 402 84 xtensa.c:749 xtensa_examine(): OCD_ID = 0733bff2
Debug: 403 84 target.c:1860 target_call_event_callbacks(): target event 21 (examine-end) for core esp32.cpu1
Debug: 404 84 target.c:5153 target_handle_event(): target(1): esp32.cpu1 (esp32) event: 21 (examine-end) action:
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 405 84 command.c:166 script_debug(): command - arm semihosting enable
Debug: 406 84 esp_xtensa_semihosting.c:49 esp_xtensa_semihosting_setup(): [esp32.cpu1] semihosting enable=1
Debug: 407 84 command.c:166 script_debug(): command - arm semihosting_resexit enable
Debug: 408 84 command.c:166 script_debug(): command - arm semihosting_basedir .
Debug: 409 84 esp32.c:508 esp32_handle_target_event(): 21
Debug: 410 84 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 21
Debug: 411 84 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 21
Debug: 412 84 xtensa.c:2392 xtensa_handle_target_event(): 21
Debug: 413 84 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu1] write smpbreak set=0x30000 clear=0x600000
Debug: 414 84 command.c:166 script_debug(): command - flash init
Debug: 415 84 tcl.c:1386 handle_flash_init_command(): Initializing flash devices...
Debug: 416 84 command.c:166 script_debug(): command - nand init
Debug: 417 84 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 418 84 command.c:166 script_debug(): command - pld init
Debug: 419 99 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 420 99 command.c:166 script_debug(): command - tpiu init
Info : 421 99 gdb_server.c:3796 gdb_target_start(): starting gdb server for esp32.cpu0 on 3333
Info : 422 99 server.c:303 add_service(): Listening on port 3333 for gdb connections
Debug: 423 99 command.c:166 script_debug(): command - reset halt
Debug: 424 99 target.c:1878 target_call_reset_callbacks(): target reset 2 (halt)
Debug: 425 99 target.c:1878 target_call_reset_callbacks(): target reset 2 (halt)
Debug: 426 99 command.c:166 script_debug(): command - expr [catch {ocd_process_reset_inner $MODE} result] == 0
Debug: 427 99 command.c:166 script_debug(): command - target names
Debug: 428 99 command.c:166 script_debug(): command - esp32.cpu0 invoke-event reset-start
Debug: 429 99 command.c:166 script_debug(): command - esp32.cpu1 invoke-event reset-start
Debug: 430 99 command.c:166 script_debug(): command - transport select
Debug: 431 99 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 432 99 command.c:166 script_debug(): command - jtag arp_init-reset
Debug: 433 99 core.c:1600 jtag_init_reset(): Initializing with hard TRST+SRST reset
Debug: 434 99 core.c:837 jtag_add_reset(): JTAG reset with TLR instead of TRST
Debug: 435 99 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 436 99 core.c:1503 jtag_init_inner(): Init JTAG chain
Debug: 437 99 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 438 99 core.c:1228 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 439 99 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 440 99 core.c:1127 jtag_examine_chain_display(): JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : 441 99 core.c:1127 jtag_examine_chain_display(): JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Debug: 442 99 core.c:1358 jtag_validate_ircapture(): IR capture validation scan
Debug: 443 99 core.c:1416 jtag_validate_ircapture(): esp32.cpu0: IR capture 0x01
Debug: 444 99 core.c:1416 jtag_validate_ircapture(): esp32.cpu1: IR capture 0x01
Debug: 445 99 command.c:166 script_debug(): command - transport select
Debug: 446 99 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 447 99 command.c:166 script_debug(): command - esp32.cpu0 cget -chain-position
Debug: 448 99 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu0
Debug: 449 99 command.c:166 script_debug(): command - esp32.cpu0 invoke-event examine-start
Debug: 450 99 command.c:166 script_debug(): command - esp32.cpu0 arp_examine allow-defer
Debug: 451 99 xtensa.c:737 xtensa_examine(): coreid = 0
Debug: 452 99 xtensa.c:749 xtensa_examine(): OCD_ID = 0733bff2
Debug: 453 99 command.c:166 script_debug(): command - esp32.cpu0 invoke-event examine-end
Debug: 454 99 target.c:5153 target_handle_event(): target(0): esp32.cpu0 (esp32) event: 21 (examine-end) action:
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 455 99 command.c:166 script_debug(): command - arm semihosting enable
Debug: 456 99 esp_xtensa_semihosting.c:49 esp_xtensa_semihosting_setup(): [esp32.cpu0] semihosting enable=1
Debug: 457 99 command.c:166 script_debug(): command - arm semihosting_resexit enable
Debug: 458 99 command.c:166 script_debug(): command - transport select
Debug: 459 99 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 460 99 command.c:166 script_debug(): command - esp32.cpu1 cget -chain-position
Debug: 461 99 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu1
Debug: 462 99 command.c:166 script_debug(): command - esp32.cpu1 invoke-event examine-start
Debug: 463 99 command.c:166 script_debug(): command - esp32.cpu1 arp_examine allow-defer
Debug: 464 99 xtensa.c:737 xtensa_examine(): coreid = 1
Debug: 465 99 xtensa.c:749 xtensa_examine(): OCD_ID = 0733bff2
Debug: 466 99 command.c:166 script_debug(): command - esp32.cpu1 invoke-event examine-end
Debug: 467 99 target.c:5153 target_handle_event(): target(1): esp32.cpu1 (esp32) event: 21 (examine-end) action:
# Need to enable to set 'semihosting_basedir'
arm semihosting enable
arm semihosting_resexit enable
if { [info exists _SEMIHOST_BASEDIR] } {
if { $_SEMIHOST_BASEDIR != "" } {
arm semihosting_basedir $_SEMIHOST_BASEDIR
}
}

Debug: 468 99 command.c:166 script_debug(): command - arm semihosting enable
Debug: 469 99 esp_xtensa_semihosting.c:49 esp_xtensa_semihosting_setup(): [esp32.cpu1] semihosting enable=1
Debug: 470 99 command.c:166 script_debug(): command - arm semihosting_resexit enable
Debug: 471 99 command.c:166 script_debug(): command - esp32.cpu0 invoke-event reset-assert-pre
Debug: 472 99 command.c:166 script_debug(): command - esp32.cpu1 invoke-event reset-assert-pre
Debug: 473 99 command.c:166 script_debug(): command - transport select
Debug: 474 99 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 475 99 command.c:166 script_debug(): command - esp32.cpu0 cget -chain-position
Debug: 476 99 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu0
Debug: 477 99 command.c:166 script_debug(): command - esp32.cpu0 arp_reset assert 1
Debug: 478 99 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 479 99 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 480 99 command.c:166 script_debug(): command - transport select
Debug: 481 99 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 482 99 command.c:166 script_debug(): command - esp32.cpu1 cget -chain-position
Debug: 483 99 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu1
Debug: 484 99 command.c:166 script_debug(): command - esp32.cpu1 arp_reset assert 1
Debug: 485 99 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 486 99 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 487 99 command.c:166 script_debug(): command - esp32.cpu0 invoke-event reset-assert-post
Debug: 488 99 target.c:5153 target_handle_event(): target(0): esp32.cpu0 (esp32) event: 12 (reset-assert-post) action: soft_reset_halt
Debug: 489 99 command.c:166 script_debug(): command - soft_reset_halt
Info : 490 99 target.c:3391 handle_soft_reset_halt_command(): [esp32.cpu0] requesting target halt and executing a soft reset
Debug: 491 99 esp_xtensa_smp.c:105 esp_xtensa_smp_soft_reset_halt(): [esp32.cpu0] begin
Debug: 492 99 esp32.c:327 esp32_soc_reset(): start
Debug: 493 99 esp32.c:383 esp32_soc_reset(): Loading stub code into RTC RAM
Debug: 494 99 target.c:2536 target_read_buffer(): reading buffer of 210 byte at 0x50000000
Debug: 495 99 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 496 99 target.c:2471 target_write_buffer(): writing buffer of 210 byte at 0x50000000
Debug: 497 115 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 498 115 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 499 115 esp32.c:400 esp32_soc_reset(): Resuming the target
Debug: 500 115 xtensa.c:1267 xtensa_resume(): [esp32.cpu0] start
Debug: 501 115 xtensa.c:1200 xtensa_prepare_resume(): [esp32.cpu0] current=0 address=0x50000004, handle_breakpoints=0, debug_execution=0)
Debug: 502 115 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 503 115 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 50000004
Debug: 504 115 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 505 115 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 3FFC045C, num =4
Debug: 506 115 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 507 115 xtensa.c:1249 xtensa_do_resume(): [esp32.cpu0] start
Debug: 508 115 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (80000000)
Debug: 509 115 target.c:1860 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu0
Debug: 510 115 esp32.c:508 esp32_handle_target_event(): 2
Debug: 511 115 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 2
Debug: 512 115 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 2
Debug: 513 115 xtensa.c:2392 xtensa_handle_target_event(): 2
Debug: 514 115 esp32.c:409 esp32_soc_reset(): resume done, waiting for the target to come alive
Debug: 515 304 esp32.c:428 esp32_soc_reset(): halting the target
Debug: 516 304 xtensa.c:1163 xtensa_halt(): [esp32.cpu0] start
Debug: 517 304 xtensa.c:1174 xtensa_halt(): [esp32.cpu0] Core status 0x80000000
Info : 518 304 xtensa.c:1754 xtensa_poll(): [esp32.cpu0] Debug controller was reset.
Debug: 519 304 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x30000 clear=0x600000
Info : 520 304 xtensa.c:1760 xtensa_poll(): [esp32.cpu0] Core was reset.
Debug: 521 304 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 522 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (80208411)
Debug: 523 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (80208411)
Debug: 524 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (80208411)
Debug: 525 304 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x500000CF, debug_reason=00000000, oldstate=00000001
Debug: 526 304 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000020, exc_cause=0, dsr=0x80208411
Info : 527 304 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x500000CF, debug_reason=00000000
Debug: 528 304 esp_xtensa.c:161 esp_xtensa_poll(): esp32.cpu0: Clear debug stubs info
Debug: 529 304 esp_xtensa_smp.c:258 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Info : 530 304 esp_xtensa_smp.c:263 esp_xtensa_smp_update_halt_gdb(): Set GDB target to 'esp32.cpu0'
Debug: 531 304 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 532 304 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 533 304 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 534 304 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32.cpu0
Debug: 535 304 esp32.c:508 esp32_handle_target_event(): 0
Debug: 536 304 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 0
Debug: 537 304 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 0
Debug: 538 304 xtensa.c:2392 xtensa_handle_target_event(): 0
Debug: 539 304 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32.cpu0
Debug: 540 304 esp32.c:508 esp32_handle_target_event(): 1
Debug: 541 304 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 1
Debug: 542 304 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 1
Debug: 543 304 xtensa.c:2392 xtensa_handle_target_event(): 1
Debug: 544 304 target.c:2778 target_write_u32(): address: 0x3ff5f064, value: 0x50d83aa1
Debug: 545 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 546 304 target.c:2778 target_write_u32(): address: 0x3ff5f048, value: 0x00000000
Debug: 547 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 548 304 target.c:2778 target_write_u32(): address: 0x3ff60064, value: 0x50d83aa1
Debug: 549 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 550 304 target.c:2778 target_write_u32(): address: 0x3ff60048, value: 0x00000000
Debug: 551 304 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 552 304 target.c:2778 target_write_u32(): address: 0x3ff480a4, value: 0x50d83aa1
Debug: 553 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 554 318 target.c:2778 target_write_u32(): address: 0x3ff4808c, value: 0x00000000
Debug: 555 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 556 318 esp32.c:432 esp32_soc_reset(): restoring RTC_SLOW_MEM
Debug: 557 318 target.c:2471 target_write_buffer(): writing buffer of 210 byte at 0x50000000
Debug: 558 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 559 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8000CC11)
Debug: 560 318 FreeRTOS.c:1300 freertos_post_reset_cleanup(): freertos_post_reset_cleanup
Debug: 561 318 xtensa.c:887 xtensa_assert_reset(): [esp32.cpu0] target_number=0, begin
Debug: 562 318 xtensa.c:887 xtensa_assert_reset(): [esp32.cpu1] target_number=1, begin
Debug: 563 318 command.c:166 script_debug(): command - esp32.cpu1 invoke-event reset-assert-post
Debug: 564 318 target.c:5153 target_handle_event(): target(1): esp32.cpu1 (esp32) event: 12 (reset-assert-post) action: soft_reset_halt
Debug: 565 318 command.c:166 script_debug(): command - soft_reset_halt
Info : 566 318 target.c:3391 handle_soft_reset_halt_command(): [esp32.cpu1] requesting target halt and executing a soft reset
Debug: 567 318 esp_xtensa_smp.c:105 esp_xtensa_smp_soft_reset_halt(): [esp32.cpu1] begin
Debug: 568 318 command.c:166 script_debug(): command - esp32.cpu0 invoke-event reset-deassert-pre
Debug: 569 318 command.c:166 script_debug(): command - esp32.cpu1 invoke-event reset-deassert-pre
Debug: 570 318 command.c:166 script_debug(): command - transport select
Debug: 571 318 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 572 318 command.c:166 script_debug(): command - esp32.cpu0 cget -chain-position
Debug: 573 318 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu0
Debug: 574 318 command.c:166 script_debug(): command - esp32.cpu0 arp_reset deassert 1
Debug: 575 318 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 576 318 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 577 318 esp_xtensa_smp.c:86 esp_xtensa_smp_deassert_reset(): [esp32.cpu0] begin
Debug: 578 318 xtensa.c:907 xtensa_deassert_reset(): [esp32.cpu0] halt=1
Debug: 579 318 command.c:166 script_debug(): command - transport select
Debug: 580 318 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 581 318 command.c:166 script_debug(): command - esp32.cpu1 cget -chain-position
Debug: 582 318 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu1
Debug: 583 318 command.c:166 script_debug(): command - esp32.cpu1 arp_reset deassert 1
Debug: 584 318 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 585 318 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 586 318 esp_xtensa_smp.c:86 esp_xtensa_smp_deassert_reset(): [esp32.cpu1] begin
Debug: 587 318 xtensa.c:907 xtensa_deassert_reset(): [esp32.cpu1] halt=1
Debug: 588 318 command.c:166 script_debug(): command - esp32.cpu0 invoke-event reset-deassert-post
Debug: 589 318 command.c:166 script_debug(): command - esp32.cpu1 invoke-event reset-deassert-post
Debug: 590 318 command.c:166 script_debug(): command - transport select
Debug: 591 318 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 592 318 command.c:166 script_debug(): command - esp32.cpu0 cget -chain-position
Debug: 593 318 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu0
Debug: 594 318 command.c:166 script_debug(): command - esp32.cpu0 was_examined
Debug: 595 318 command.c:166 script_debug(): command - esp32.cpu0 arp_waitstate halted 1000
Info : 596 318 xtensa.c:1760 xtensa_poll(): [esp32.cpu0] Core was reset.
Debug: 597 318 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 598 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (81A0CC11)
Debug: 599 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (81A0CC11)
Debug: 600 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (81A0CC11)
Debug: 601 318 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x40000400, debug_reason=00000000, oldstate=00000001
Debug: 602 318 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000020, exc_cause=0, dsr=0x81a0cc11
Info : 603 318 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x40000400, debug_reason=00000000
Debug: 604 318 esp_xtensa.c:161 esp_xtensa_poll(): esp32.cpu0: Clear debug stubs info
Debug: 605 318 esp_xtensa_smp.c:258 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Debug: 606 318 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 607 318 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 608 318 esp_xtensa_smp.c:286 esp_xtensa_smp_update_halt_gdb(): Poll target 'esp32.cpu1'
Info : 609 318 xtensa.c:1754 xtensa_poll(): [esp32.cpu1] Debug controller was reset.
Debug: 610 318 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu1] write smpbreak set=0x30000 clear=0x600000
Info : 611 318 xtensa.c:1760 xtensa_poll(): [esp32.cpu1] Core was reset.
Debug: 612 318 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu1] start
Debug: 613 318 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (80A08411)
Debug: 614 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (80A08411)
Debug: 615 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (80A08411)
Debug: 616 334 xtensa.c:1808 xtensa_poll(): [esp32.cpu1] Target halted, pc=0x40000400, debug_reason=00000000, oldstate=00000001
Debug: 617 334 xtensa.c:1812 xtensa_poll(): [esp32.cpu1] Halt reason=0x00000020, exc_cause=0, dsr=0x80a08411
Info : 618 334 xtensa.c:1814 xtensa_poll(): [esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
Debug: 619 334 esp_xtensa.c:161 esp_xtensa_poll(): esp32.cpu1: Clear debug stubs info
Debug: 620 334 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32.cpu1
Debug: 621 334 esp32.c:508 esp32_handle_target_event(): 0
Debug: 622 334 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 0
Debug: 623 334 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 0
Debug: 624 334 xtensa.c:2392 xtensa_handle_target_event(): 0
Debug: 625 334 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32.cpu1
Debug: 626 334 esp32.c:508 esp32_handle_target_event(): 1
Debug: 627 334 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 1
Debug: 628 334 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 1
Debug: 629 334 xtensa.c:2392 xtensa_handle_target_event(): 1
Debug: 630 334 target.c:2778 target_write_u32(): address: 0x3ff5f064, value: 0x50d83aa1
Debug: 631 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 632 334 target.c:2778 target_write_u32(): address: 0x3ff5f048, value: 0x00000000
Debug: 633 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 634 334 target.c:2778 target_write_u32(): address: 0x3ff60064, value: 0x50d83aa1
Debug: 635 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 636 334 target.c:2778 target_write_u32(): address: 0x3ff60048, value: 0x00000000
Debug: 637 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 638 334 target.c:2778 target_write_u32(): address: 0x3ff480a4, value: 0x50d83aa1
Debug: 639 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 640 334 target.c:2778 target_write_u32(): address: 0x3ff4808c, value: 0x00000000
Debug: 641 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu1] DSR (8080CC11)
Debug: 642 334 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 643 334 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32.cpu0
Debug: 644 334 esp32.c:508 esp32_handle_target_event(): 0
Debug: 645 334 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 0
Debug: 646 334 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 0
Debug: 647 334 xtensa.c:2392 xtensa_handle_target_event(): 0
Debug: 648 334 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32.cpu0
Debug: 649 334 esp32.c:508 esp32_handle_target_event(): 1
Debug: 650 334 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 1
Debug: 651 334 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 1
Debug: 652 334 xtensa.c:2392 xtensa_handle_target_event(): 1
Debug: 653 334 target.c:2778 target_write_u32(): address: 0x3ff5f064, value: 0x50d83aa1
Debug: 654 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 655 334 target.c:2778 target_write_u32(): address: 0x3ff5f048, value: 0x00000000
Debug: 656 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 657 334 target.c:2778 target_write_u32(): address: 0x3ff60064, value: 0x50d83aa1
Debug: 658 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 659 334 target.c:2778 target_write_u32(): address: 0x3ff60048, value: 0x00000000
Debug: 660 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 661 334 target.c:2778 target_write_u32(): address: 0x3ff480a4, value: 0x50d83aa1
Debug: 662 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 663 334 target.c:2778 target_write_u32(): address: 0x3ff4808c, value: 0x00000000
Debug: 664 334 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 665 334 command.c:166 script_debug(): command - esp32.cpu0 curstate
Debug: 666 334 command.c:166 script_debug(): command - transport select
Debug: 667 334 command.c:166 script_debug(): command - expr [ string first "jtag" $_TRANSPORT ] != -1
Debug: 668 334 command.c:166 script_debug(): command - esp32.cpu1 cget -chain-position
Debug: 669 334 command.c:166 script_debug(): command - jtag tapisenabled esp32.cpu1
Debug: 670 334 command.c:166 script_debug(): command - esp32.cpu1 was_examined
Debug: 671 334 command.c:166 script_debug(): command - esp32.cpu1 arp_waitstate halted 1000
Debug: 672 334 command.c:166 script_debug(): command - esp32.cpu1 curstate
Debug: 673 334 command.c:166 script_debug(): command - esp32.cpu0 invoke-event reset-end
Debug: 674 334 command.c:166 script_debug(): command - esp32.cpu1 invoke-event reset-end
Debug: 675 349 command.c:166 script_debug(): command - flash erase_address 0x1000 61440
Debug: 676 349 esp_flash.c:948 esp_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32.cpu1' - 'halted'
Debug: 677 349 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 678 349 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 679 349 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x0 clear=0x630000
Debug: 680 349 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=0, state=2
Debug: 681 349 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x40091994, 2 sections
Debug: 682 349 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 9723, flags 1
Debug: 683 349 target.c:2065 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x40090000
Debug: 684 349 target.c:2119 alloc_working_area_try_do(): allocated new working area of 9724 bytes at address 0x40090000
Debug: 685 381 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 686 381 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 687 381 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 688 381 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090000
Debug: 689 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 690 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090200
Debug: 691 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 692 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090400
Debug: 693 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 694 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090600
Debug: 695 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 696 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090800
Debug: 697 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 698 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090a00
Debug: 699 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 700 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090c00
Debug: 701 396 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 702 396 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090e00
Debug: 703 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 704 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091000
Debug: 705 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 706 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091200
Debug: 707 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 708 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091400
Debug: 709 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 710 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091600
Debug: 711 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 712 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091800
Debug: 713 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 714 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091a00
Debug: 715 412 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 716 412 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091c00
Debug: 717 428 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 718 428 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091e00
Debug: 719 428 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 720 428 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092000
Debug: 721 428 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 722 428 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092200
Debug: 723 428 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 724 428 target.c:2471 target_write_buffer(): writing buffer of 507 byte at 0x40092400
Debug: 725 428 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 726 428 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 727 428 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 1060, flags 0
Debug: 728 428 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 1060 -> 1060
Debug: 729 428 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 53 -> 56
Debug: 730 428 target.c:2065 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x3ffc0000
Debug: 731 428 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1116 bytes at address 0x3ffc0000
Debug: 732 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 733 443 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 734 443 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 735 443 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0000
Debug: 736 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 737 443 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0200
Debug: 738 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 739 443 target.c:2471 target_write_buffer(): writing buffer of 36 byte at 0x3ffc0400
Debug: 740 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 741 443 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1300 bytes at address 0x3ffc045c
Debug: 742 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 743 443 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 744 443 target.c:1986 print_wa_layout(): b* 0x3ffc045c-0x3ffc096f (1300 bytes)
Debug: 745 443 target.c:1986 print_wa_layout(): 0x3ffc0970-0x3ffd7fff (95888 bytes)
Debug: 746 443 target.c:2119 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x400925fc
Debug: 747 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 748 443 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 749 443 target.c:1986 print_wa_layout(): b* 0x400925fc-0x40092617 (28 bytes)
Debug: 750 443 target.c:1986 print_wa_layout(): 0x40092618-0x40093fff (6632 bytes)
Debug: 751 443 target.c:2471 target_write_buffer(): writing buffer of 28 byte at 0x400925fc
Debug: 752 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 753 443 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 93.803 ms
Debug: 754 443 xtensa_algorithm.c:114 xtensa_algo_init(): reg params count 9 (6/3).
Debug: 755 443 xtensa_algorithm.c:61 xtensa_algo_regs_init_start(): Check stack addr 0x3ffc0970
Debug: 756 443 xtensa_algorithm.c:129 xtensa_algo_init(): Set arg[0] = 5 (a2)
Debug: 757 443 xtensa_algorithm.c:140 xtensa_algo_init(): Set arg[1] = -1 (a3)
Debug: 758 443 xtensa_algorithm.c:140 xtensa_algo_init(): Set arg[2] = 0 (a4)
Debug: 759 443 target.c:2119 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x3ffc0970
Debug: 760 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 761 443 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 762 443 target.c:1986 print_wa_layout(): b* 0x3ffc045c-0x3ffc096f (1300 bytes)
Debug: 763 443 target.c:1986 print_wa_layout(): b* 0x3ffc0970-0x3ffc098b (28 bytes)
Debug: 764 443 target.c:1986 print_wa_layout(): 0x3ffc098c-0x3ffd7fff (95860 bytes)
Debug: 765 443 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x400925fc, stack 1300 bytes @ 0x3ffc0970
Debug: 766 443 xtensa.c:1267 xtensa_resume(): [esp32.cpu0] start
Debug: 767 443 xtensa.c:1200 xtensa_prepare_resume(): [esp32.cpu0] current=0 address=0x400925fc, handle_breakpoints=1, debug_execution=1)
Debug: 768 443 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 769 443 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 400925FC
Debug: 770 443 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowbase val 00000000
Debug: 771 443 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowstart val 00000001
Debug: 772 443 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 00060025
Debug: 773 443 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 774 443 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a0 value 00000000, num =1
Debug: 775 443 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 3FFC0960, num =2
Debug: 776 443 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000005, num =3
Debug: 777 443 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value FFFFFFFF, num =4
Debug: 778 443 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a4 value 3FFC0970, num =5
Debug: 779 443 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 40091994, num =9
Debug: 780 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 781 443 xtensa.c:1249 xtensa_do_resume(): [esp32.cpu0] start
Debug: 782 443 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC01)
Debug: 783 443 target.c:1860 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu0
Debug: 784 443 esp32.c:508 esp32_handle_target_event(): 2
Debug: 785 443 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 2
Debug: 786 443 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 2
Debug: 787 443 xtensa.c:2392 xtensa_handle_target_event(): 2
Debug: 788 443 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 789 459 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 790 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 791 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 792 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 793 459 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x40092612, debug_reason=00000001, oldstate=00000004
Debug: 794 459 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000008, exc_cause=0, dsr=0x8080cc11
Info : 795 459 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Debug: 796 459 esp_xtensa_smp.c:258 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Debug: 797 459 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 798 459 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 799 459 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 800 459 target.c:1860 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32.cpu0
Debug: 801 459 esp32.c:508 esp32_handle_target_event(): 17
Debug: 802 459 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 17
Debug: 803 459 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 17
Debug: 804 459 xtensa.c:2392 xtensa_handle_target_event(): 17
Debug: 805 459 xtensa.c:2170 xtensa_wait_algorithm(): Read mem params
Debug: 806 459 xtensa.c:2172 xtensa_wait_algorithm(): Check mem param @ 0x3ffc0970
Debug: 807 459 xtensa.c:2174 xtensa_wait_algorithm(): Read mem param @ 0x3ffc0970
Debug: 808 459 target.c:2536 target_read_buffer(): reading buffer of 28 byte at 0x3ffc0970
Debug: 809 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 810 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a15: 0x0000ffff -> 0x00000000
Debug: 811 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a14: 0x00000020 -> 0x00000000
Debug: 812 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a13: 0x00400000 -> 0x00000000
Debug: 813 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a10: 0xfffffffa -> 0x00000000
Debug: 814 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a9: 0x3ffc0870 -> 0x00000000
Debug: 815 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a8: 0x80092610 -> 0x00000000
Debug: 816 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a4: 0x3ffc0970 -> 0x00000000
Debug: 817 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a3: 0xffffffff -> 0x00000000
Debug: 818 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a2: 0xfffffffa -> 0x00000000
Debug: 819 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a1: 0x3ffc0960 -> 0x00000000
Debug: 820 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ccount: 0x00003c2e -> 0x00000004
Debug: 821 459 xtensa.c:2194 xtensa_wait_algorithm(): Skip restoring register debugcause: 0x00000008 -> 0x00000020
Debug: 822 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register eps6: 0x00060025 -> 0x0000001f
Debug: 823 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register epc6: 0x40092612 -> 0x40000400
Debug: 824 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ps: 0x00060025 -> 0x0000001f
Debug: 825 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register configid0: 0x40092612 -> 0x40000400
Debug: 826 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register sar: 0x00000019 -> 0x00000000
Debug: 827 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register lend: 0x4000c2f6 -> 0x00000000
Debug: 828 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register lbeg: 0x4000c2e0 -> 0x00000000
Debug: 829 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar45: 0x08000000 -> 0x00000000
Debug: 830 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar43: 0x3ff42000 -> 0x00000000
Debug: 831 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar42: 0x3ffc0820 -> 0x00000000
Debug: 832 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar41: 0x3ff42010 -> 0x00000000
Debug: 833 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar39: 0x00000007 -> 0x00000000
Debug: 834 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar37: 0x08000000 -> 0x00000000
Debug: 835 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar35: 0xfffffff7 -> 0x00000000
Debug: 836 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar34: 0x3ff00044 -> 0x00000000
Debug: 837 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar33: 0x000008ef -> 0x00000000
Debug: 838 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar32: 0xffffffc0 -> 0x00000000
Debug: 839 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar31: 0xffffffff -> 0x00000000
Debug: 840 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar30: 0xffffffff -> 0x00000000
Debug: 841 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar29: 0x3ffc08b8 -> 0x00000000
Debug: 842 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar28: 0x00000020 -> 0x00000000
Debug: 843 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar27: 0x0000002f -> 0x00000000
Debug: 844 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar25: 0x3ffc0810 -> 0x00000000
Debug: 845 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar24: 0x800906bd -> 0x00000000
Debug: 846 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar23: 0x3ff10000 -> 0x00000000
Debug: 847 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar21: 0x00000001 -> 0x00000000
Debug: 848 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar20: 0x3ff10000 -> 0x00000000
Debug: 849 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar19: 0x00000001 -> 0x00000000
Debug: 850 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar17: 0x3ffc0830 -> 0x00000000
Debug: 851 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar16: 0x80091d5b -> 0x00000000
Debug: 852 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar15: 0x0000ffff -> 0x00000000
Debug: 853 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar14: 0x00000020 -> 0x00000000
Debug: 854 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar13: 0x00400000 -> 0x00000000
Debug: 855 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar10: 0xfffffffa -> 0x00000000
Debug: 856 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar9: 0x3ffc0870 -> 0x00000000
Debug: 857 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar8: 0x80092610 -> 0x00000000
Debug: 858 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar4: 0x3ffc0970 -> 0x00000000
Debug: 859 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar3: 0xffffffff -> 0x00000000
Debug: 860 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar2: 0xfffffffa -> 0x00000000
Debug: 861 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar1: 0x3ffc0960 -> 0x00000000
Debug: 862 459 xtensa.c:2204 xtensa_wait_algorithm(): restoring register pc: 0x40092612 -> 0x40000400
Debug: 863 459 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 864 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 40000400
Debug: 865 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg lbeg val 00000000
Debug: 866 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg lend val 00000000
Debug: 867 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg sar val 00000000
Debug: 868 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg configid0 val 40000400
Debug: 869 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 0000001F
Debug: 870 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg epc6 val 40000400
Debug: 871 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg eps6 val 0000001F
Debug: 872 459 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ccount val 00000004
Debug: 873 459 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 874 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 00000000, num =2
Debug: 875 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000000, num =3
Debug: 876 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00000000, num =4
Debug: 877 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a4 value 00000000, num =5
Debug: 878 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 00000000, num =9
Debug: 879 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a9 value 00000000, num =10
Debug: 880 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a10 value 00000000, num =11
Debug: 881 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a13 value 00000000, num =14
Debug: 882 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a14 value 00000000, num =15
Debug: 883 459 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a15 value 00000000, num =16
Debug: 884 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar1 value 00000000, num =1
Debug: 885 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar2 value 00000000, num =2
Debug: 886 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar3 value 00000000, num =3
Debug: 887 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar4 value 00000000, num =4
Debug: 888 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar8 value 00000000, num =8
Debug: 889 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar9 value 00000000, num =9
Debug: 890 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar10 value 00000000, num =10
Debug: 891 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar13 value 00000000, num =13
Debug: 892 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar14 value 00000000, num =14
Debug: 893 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar15 value 00000000, num =15
Debug: 894 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar16 value 00000000, num =16
Debug: 895 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar17 value 00000000, num =17
Debug: 896 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar19 value 00000000, num =19
Debug: 897 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar20 value 00000000, num =20
Debug: 898 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar21 value 00000000, num =21
Debug: 899 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar23 value 00000000, num =23
Debug: 900 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar24 value 00000000, num =24
Debug: 901 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar25 value 00000000, num =25
Debug: 902 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar27 value 00000000, num =27
Debug: 903 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar28 value 00000000, num =28
Debug: 904 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar29 value 00000000, num =29
Debug: 905 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar30 value 00000000, num =30
Debug: 906 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar31 value 00000000, num =31
Debug: 907 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar32 value 00000000, num =32
Debug: 908 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar33 value 00000000, num =33
Debug: 909 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar34 value 00000000, num =34
Debug: 910 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar35 value 00000000, num =35
Debug: 911 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar37 value 00000000, num =37
Debug: 912 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar39 value 00000000, num =39
Debug: 913 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar41 value 00000000, num =41
Debug: 914 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar42 value 00000000, num =42
Debug: 915 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar43 value 00000000, num =43
Debug: 916 459 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar45 value 00000000, num =45
Debug: 917 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 918 459 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0xfffffffa
Debug: 919 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 920 459 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x3ffc0970
Debug: 921 459 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 922 459 target.c:1986 print_wa_layout(): b* 0x3ffc045c-0x3ffc096f (1300 bytes)
Debug: 923 459 target.c:1986 print_wa_layout(): 0x3ffc0970-0x3ffd7fff (95888 bytes)
Debug: 924 459 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 925 459 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x400925fc
Debug: 926 459 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 927 459 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 928 475 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 929 475 target.c:2206 target_free_working_area_restore(): freed 1300 bytes of working area at address 0x3ffc045c
Debug: 930 475 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 931 475 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 932 507 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 933 507 target.c:2206 target_free_working_area_restore(): freed 9724 bytes of working area at address 0x40090000
Debug: 934 507 target.c:1986 print_wa_layout(): 0x40090000-0x40093fff (16384 bytes)
Debug: 935 507 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 936 507 target.c:2206 target_free_working_area_restore(): freed 1116 bytes of working area at address 0x3ffc0000
Debug: 937 507 target.c:1986 print_wa_layout(): 0x3ffc0000-0x3ffd7fff (98304 bytes)
Debug: 938 507 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x30000 clear=0x600000
Debug: 939 507 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=30000, state=2
Error: 940 507 esp_flash.c:382 esp_flash_get_mappings(): Failed to get flash maps (4294967290)!
Warn : 941 507 esp_flash.c:960 esp_flash_probe(): Failed to get flash mappings (-4)!
Debug: 942 507 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 943 507 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 944 507 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x0 clear=0x630000
Debug: 945 507 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=0, state=2
Debug: 946 507 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x40091994, 2 sections
Debug: 947 507 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 9723, flags 1
Debug: 948 507 target.c:2119 alloc_working_area_try_do(): allocated new working area of 9724 bytes at address 0x40090000
Debug: 949 584 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 950 584 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 951 584 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 952 584 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090000
Debug: 953 584 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 954 584 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090200
Debug: 955 584 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 956 584 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090400
Debug: 957 584 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 958 584 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090600
Debug: 959 584 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 960 584 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090800
Debug: 961 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 962 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090a00
Debug: 963 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 964 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090c00
Debug: 965 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 966 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090e00
Debug: 967 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 968 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091000
Debug: 969 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 970 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091200
Debug: 971 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 972 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091400
Debug: 973 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 974 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091600
Debug: 975 599 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 976 599 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091800
Debug: 977 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 978 615 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091a00
Debug: 979 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 980 615 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091c00
Debug: 981 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 982 615 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091e00
Debug: 983 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 984 615 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092000
Debug: 985 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 986 615 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092200
Debug: 987 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 988 615 target.c:2471 target_write_buffer(): writing buffer of 507 byte at 0x40092400
Debug: 989 615 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 990 631 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 991 631 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 1060, flags 0
Debug: 992 631 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 1060 -> 1060
Debug: 993 631 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 53 -> 56
Debug: 994 631 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1116 bytes at address 0x3ffc0000
Debug: 995 631 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 996 631 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 997 631 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 998 631 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0000
Debug: 999 631 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1000 631 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0200
Debug: 1001 631 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1002 631 target.c:2471 target_write_buffer(): writing buffer of 36 byte at 0x3ffc0400
Debug: 1003 631 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1004 631 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3ffc045c
Debug: 1005 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1006 646 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1007 646 target.c:1986 print_wa_layout(): b* 0x3ffc045c-0x3ffc085b (1024 bytes)
Debug: 1008 646 target.c:1986 print_wa_layout(): 0x3ffc085c-0x3ffd7fff (96164 bytes)
Debug: 1009 646 target.c:2119 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x400925fc
Debug: 1010 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1011 646 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1012 646 target.c:1986 print_wa_layout(): b* 0x400925fc-0x40092617 (28 bytes)
Debug: 1013 646 target.c:1986 print_wa_layout(): 0x40092618-0x40093fff (6632 bytes)
Debug: 1014 646 target.c:2471 target_write_buffer(): writing buffer of 28 byte at 0x400925fc
Debug: 1015 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1016 646 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 138.971 ms
Debug: 1017 646 xtensa_algorithm.c:114 xtensa_algo_init(): reg params count 7 (6/1).
Debug: 1018 646 xtensa_algorithm.c:61 xtensa_algo_regs_init_start(): Check stack addr 0x3ffc085c
Debug: 1019 646 xtensa_algorithm.c:64 xtensa_algo_regs_init_start(): Adjust stack addr to 0x3ffc0850
Debug: 1020 646 xtensa_algorithm.c:129 xtensa_algo_init(): Set arg[0] = 4 (a2)
Debug: 1021 646 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x400925fc, stack 1024 bytes @ 0x3ffc085c
Debug: 1022 646 xtensa.c:1267 xtensa_resume(): [esp32.cpu0] start
Debug: 1023 646 xtensa.c:1200 xtensa_prepare_resume(): [esp32.cpu0] current=0 address=0x400925fc, handle_breakpoints=1, debug_execution=1)
Debug: 1024 646 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 1025 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 400925FC
Debug: 1026 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowbase val 00000000
Debug: 1027 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowstart val 00000001
Debug: 1028 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 00060025
Debug: 1029 646 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 1030 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a0 value 00000000, num =1
Debug: 1031 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 3FFC0840, num =2
Debug: 1032 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000004, num =3
Debug: 1033 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00000000, num =4
Debug: 1034 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 40091994, num =9
Debug: 1035 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1036 646 xtensa.c:1249 xtensa_do_resume(): [esp32.cpu0] start
Debug: 1037 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1038 646 target.c:1860 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu0
Debug: 1039 646 esp32.c:508 esp32_handle_target_event(): 2
Debug: 1040 646 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 2
Debug: 1041 646 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 2
Debug: 1042 646 xtensa.c:2392 xtensa_handle_target_event(): 2
Debug: 1043 646 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 1044 646 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 1045 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1046 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1047 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1048 646 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x40092612, debug_reason=00000001, oldstate=00000004
Debug: 1049 646 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000008, exc_cause=0, dsr=0x8080cc11
Info : 1050 646 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Debug: 1051 646 esp_xtensa_smp.c:258 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Debug: 1052 646 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 1053 646 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 1054 646 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 1055 646 target.c:1860 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32.cpu0
Debug: 1056 646 esp32.c:508 esp32_handle_target_event(): 17
Debug: 1057 646 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 17
Debug: 1058 646 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 17
Debug: 1059 646 xtensa.c:2392 xtensa_handle_target_event(): 17
Debug: 1060 646 xtensa.c:2170 xtensa_wait_algorithm(): Read mem params
Debug: 1061 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a14: 0x3ffc0304 -> 0x00000000
Debug: 1062 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a10: 0x00400000 -> 0x00000000
Debug: 1063 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a9: 0x3ffc0750 -> 0x00000000
Debug: 1064 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a8: 0x80092610 -> 0x00000000
Debug: 1065 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a2: 0x00400000 -> 0x00000000
Debug: 1066 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a1: 0x3ffc0840 -> 0x00000000
Debug: 1067 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ccount: 0x00000865 -> 0x00000004
Debug: 1068 646 xtensa.c:2194 xtensa_wait_algorithm(): Skip restoring register debugcause: 0x00000008 -> 0x00000020
Debug: 1069 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register eps6: 0x00060025 -> 0x0000001f
Debug: 1070 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register epc6: 0x40092612 -> 0x40000400
Debug: 1071 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ps: 0x00060025 -> 0x0000001f
Debug: 1072 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register configid0: 0x40092612 -> 0x40000400
Debug: 1073 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar31: 0x00040000 -> 0x00000000
Debug: 1074 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar30: 0x80000040 -> 0x00000000
Debug: 1075 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar29: 0x70000000 -> 0x00000000
Debug: 1076 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar28: 0x3ff42000 -> 0x00000000
Debug: 1077 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar27: 0x3ff42010 -> 0x00000000
Debug: 1078 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar26: 0x3ffae270 -> 0x00000000
Debug: 1079 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar24: 0x3ff42024 -> 0x00000000
Debug: 1080 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar22: 0x80000040 -> 0x00000000
Debug: 1081 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar21: 0x5c000007 -> 0x00000000
Debug: 1082 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar20: 0x70000000 -> 0x00000000
Debug: 1083 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar19: 0x00400000 -> 0x00000000
Debug: 1084 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar17: 0x3ffc0730 -> 0x00000000
Debug: 1085 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar16: 0x80091b40 -> 0x00000000
Debug: 1086 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar14: 0x3ffc0304 -> 0x00000000
Debug: 1087 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar10: 0x00400000 -> 0x00000000
Debug: 1088 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar9: 0x3ffc0750 -> 0x00000000
Debug: 1089 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar8: 0x80092610 -> 0x00000000
Debug: 1090 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar2: 0x00400000 -> 0x00000000
Debug: 1091 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar1: 0x3ffc0840 -> 0x00000000
Debug: 1092 646 xtensa.c:2204 xtensa_wait_algorithm(): restoring register pc: 0x40092612 -> 0x40000400
Debug: 1093 646 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 1094 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 40000400
Debug: 1095 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg configid0 val 40000400
Debug: 1096 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 0000001F
Debug: 1097 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg epc6 val 40000400
Debug: 1098 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg eps6 val 0000001F
Debug: 1099 646 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ccount val 00000004
Debug: 1100 646 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 1101 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 00000000, num =2
Debug: 1102 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000000, num =3
Debug: 1103 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00000000, num =4
Debug: 1104 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 00000000, num =9
Debug: 1105 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a9 value 00000000, num =10
Debug: 1106 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a10 value 00000000, num =11
Debug: 1107 646 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a14 value 00000000, num =15
Debug: 1108 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar1 value 00000000, num =1
Debug: 1109 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar2 value 00000000, num =2
Debug: 1110 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar8 value 00000000, num =8
Debug: 1111 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar9 value 00000000, num =9
Debug: 1112 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar10 value 00000000, num =10
Debug: 1113 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar14 value 00000000, num =14
Debug: 1114 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar16 value 00000000, num =16
Debug: 1115 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar17 value 00000000, num =17
Debug: 1116 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar19 value 00000000, num =19
Debug: 1117 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar20 value 00000000, num =20
Debug: 1118 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar21 value 00000000, num =21
Debug: 1119 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar22 value 00000000, num =22
Debug: 1120 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar24 value 00000000, num =24
Debug: 1121 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar26 value 00000000, num =26
Debug: 1122 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar27 value 00000000, num =27
Debug: 1123 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar28 value 00000000, num =28
Debug: 1124 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar29 value 00000000, num =29
Debug: 1125 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar30 value 00000000, num =30
Debug: 1126 646 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar31 value 00000000, num =31
Debug: 1127 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1128 646 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0x400000
Debug: 1129 646 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1130 646 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x400925fc
Debug: 1131 646 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1132 646 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 1133 662 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1134 662 target.c:2206 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3ffc045c
Debug: 1135 662 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1136 662 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 1137 693 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1138 693 target.c:2206 target_free_working_area_restore(): freed 9724 bytes of working area at address 0x40090000
Debug: 1139 693 target.c:1986 print_wa_layout(): 0x40090000-0x40093fff (16384 bytes)
Debug: 1140 693 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1141 693 target.c:2206 target_free_working_area_restore(): freed 1116 bytes of working area at address 0x3ffc0000
Debug: 1142 693 target.c:1986 print_wa_layout(): 0x3ffc0000-0x3ffd7fff (98304 bytes)
Debug: 1143 693 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x30000 clear=0x600000
Debug: 1144 693 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=30000, state=2
Debug: 1145 693 esp_flash.c:344 esp_flash_get_size(): esp_flash_get_size size 0x400000
Debug: 1146 693 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 1147 693 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1148 693 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x0 clear=0x630000
Debug: 1149 693 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=0, state=2
Debug: 1150 693 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x40091994, 2 sections
Debug: 1151 693 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 9723, flags 1
Debug: 1152 693 target.c:2119 alloc_working_area_try_do(): allocated new working area of 9724 bytes at address 0x40090000
Debug: 1153 741 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1154 741 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1155 741 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 1156 741 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090000
Debug: 1157 741 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1158 741 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090200
Debug: 1159 741 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1160 741 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090400
Debug: 1161 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1162 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090600
Debug: 1163 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1164 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090800
Debug: 1165 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1166 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090a00
Debug: 1167 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1168 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090c00
Debug: 1169 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1170 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090e00
Debug: 1171 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1172 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091000
Debug: 1173 756 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1174 756 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091200
Debug: 1175 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1176 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091400
Debug: 1177 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1178 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091600
Debug: 1179 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1180 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091800
Debug: 1181 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1182 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091a00
Debug: 1183 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1184 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091c00
Debug: 1185 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1186 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091e00
Debug: 1187 771 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1188 771 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092000
Debug: 1189 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1190 787 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092200
Debug: 1191 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1192 787 target.c:2471 target_write_buffer(): writing buffer of 507 byte at 0x40092400
Debug: 1193 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1194 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1195 787 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 1060, flags 0
Debug: 1196 787 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 1060 -> 1060
Debug: 1197 787 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 53 -> 56
Debug: 1198 787 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1116 bytes at address 0x3ffc0000
Debug: 1199 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1200 787 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1201 787 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 1202 787 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0000
Debug: 1203 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1204 787 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0200
Debug: 1205 787 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1206 787 target.c:2471 target_write_buffer(): writing buffer of 36 byte at 0x3ffc0400
Debug: 1207 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1208 803 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3ffc045c
Debug: 1209 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1210 803 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1211 803 target.c:1986 print_wa_layout(): b* 0x3ffc045c-0x3ffc085b (1024 bytes)
Debug: 1212 803 target.c:1986 print_wa_layout(): 0x3ffc085c-0x3ffd7fff (96164 bytes)
Debug: 1213 803 target.c:2119 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x400925fc
Debug: 1214 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1215 803 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1216 803 target.c:1986 print_wa_layout(): b* 0x400925fc-0x40092617 (28 bytes)
Debug: 1217 803 target.c:1986 print_wa_layout(): 0x40092618-0x40093fff (6632 bytes)
Debug: 1218 803 target.c:2471 target_write_buffer(): writing buffer of 28 byte at 0x400925fc
Debug: 1219 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1220 803 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 109.344 ms
Debug: 1221 803 xtensa_algorithm.c:114 xtensa_algo_init(): reg params count 7 (6/1).
Debug: 1222 803 xtensa_algorithm.c:61 xtensa_algo_regs_init_start(): Check stack addr 0x3ffc085c
Debug: 1223 803 xtensa_algorithm.c:64 xtensa_algo_regs_init_start(): Adjust stack addr to 0x3ffc0850
Debug: 1224 803 xtensa_algorithm.c:129 xtensa_algo_init(): Set arg[0] = 4 (a2)
Debug: 1225 803 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x400925fc, stack 1024 bytes @ 0x3ffc085c
Debug: 1226 803 xtensa.c:1267 xtensa_resume(): [esp32.cpu0] start
Debug: 1227 803 xtensa.c:1200 xtensa_prepare_resume(): [esp32.cpu0] current=0 address=0x400925fc, handle_breakpoints=1, debug_execution=1)
Debug: 1228 803 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 1229 803 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 400925FC
Debug: 1230 803 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowbase val 00000000
Debug: 1231 803 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowstart val 00000001
Debug: 1232 803 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 00060025
Debug: 1233 803 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 1234 803 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a0 value 00000000, num =1
Debug: 1235 803 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 3FFC0840, num =2
Debug: 1236 803 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000004, num =3
Debug: 1237 803 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00000000, num =4
Debug: 1238 803 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 40091994, num =9
Debug: 1239 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1240 803 xtensa.c:1249 xtensa_do_resume(): [esp32.cpu0] start
Debug: 1241 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1242 803 target.c:1860 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu0
Debug: 1243 803 esp32.c:508 esp32_handle_target_event(): 2
Debug: 1244 803 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 2
Debug: 1245 803 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 2
Debug: 1246 803 xtensa.c:2392 xtensa_handle_target_event(): 2
Debug: 1247 803 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 1248 803 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 1249 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1250 803 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1251 818 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1252 818 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x40092612, debug_reason=00000001, oldstate=00000004
Debug: 1253 818 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000008, exc_cause=0, dsr=0x8080cc11
Info : 1254 818 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Debug: 1255 818 esp_xtensa_smp.c:258 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Debug: 1256 818 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 1257 818 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 1258 818 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 1259 818 target.c:1860 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32.cpu0
Debug: 1260 818 esp32.c:508 esp32_handle_target_event(): 17
Debug: 1261 818 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 17
Debug: 1262 818 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 17
Debug: 1263 818 xtensa.c:2392 xtensa_handle_target_event(): 17
Debug: 1264 818 xtensa.c:2170 xtensa_wait_algorithm(): Read mem params
Debug: 1265 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a14: 0x3ffc0304 -> 0x00000000
Debug: 1266 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a10: 0x00400000 -> 0x00000000
Debug: 1267 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a9: 0x3ffc0750 -> 0x00000000
Debug: 1268 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a8: 0x80092610 -> 0x00000000
Debug: 1269 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a2: 0x00400000 -> 0x00000000
Debug: 1270 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a1: 0x3ffc0840 -> 0x00000000
Debug: 1271 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ccount: 0x00000865 -> 0x00000004
Debug: 1272 818 xtensa.c:2194 xtensa_wait_algorithm(): Skip restoring register debugcause: 0x00000008 -> 0x00000020
Debug: 1273 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register eps6: 0x00060025 -> 0x0000001f
Debug: 1274 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register epc6: 0x40092612 -> 0x40000400
Debug: 1275 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ps: 0x00060025 -> 0x0000001f
Debug: 1276 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register configid0: 0x40092612 -> 0x40000400
Debug: 1277 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar31: 0x00040000 -> 0x00000000
Debug: 1278 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar30: 0x80000040 -> 0x00000000
Debug: 1279 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar29: 0x70000000 -> 0x00000000
Debug: 1280 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar28: 0x3ff42000 -> 0x00000000
Debug: 1281 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar27: 0x3ff42010 -> 0x00000000
Debug: 1282 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar26: 0x3ffae270 -> 0x00000000
Debug: 1283 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar24: 0x3ff42024 -> 0x00000000
Debug: 1284 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar22: 0x80000040 -> 0x00000000
Debug: 1285 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar21: 0x5c000007 -> 0x00000000
Debug: 1286 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar20: 0x70000000 -> 0x00000000
Debug: 1287 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar19: 0x00400000 -> 0x00000000
Debug: 1288 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar17: 0x3ffc0730 -> 0x00000000
Debug: 1289 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar16: 0x80091b40 -> 0x00000000
Debug: 1290 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar14: 0x3ffc0304 -> 0x00000000
Debug: 1291 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar10: 0x00400000 -> 0x00000000
Debug: 1292 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar9: 0x3ffc0750 -> 0x00000000
Debug: 1293 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar8: 0x80092610 -> 0x00000000
Debug: 1294 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar2: 0x00400000 -> 0x00000000
Debug: 1295 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar1: 0x3ffc0840 -> 0x00000000
Debug: 1296 818 xtensa.c:2204 xtensa_wait_algorithm(): restoring register pc: 0x40092612 -> 0x40000400
Debug: 1297 818 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 1298 818 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 40000400
Debug: 1299 818 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg configid0 val 40000400
Debug: 1300 818 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 0000001F
Debug: 1301 818 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg epc6 val 40000400
Debug: 1302 818 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg eps6 val 0000001F
Debug: 1303 818 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ccount val 00000004
Debug: 1304 818 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 1305 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 00000000, num =2
Debug: 1306 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000000, num =3
Debug: 1307 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00000000, num =4
Debug: 1308 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 00000000, num =9
Debug: 1309 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a9 value 00000000, num =10
Debug: 1310 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a10 value 00000000, num =11
Debug: 1311 818 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a14 value 00000000, num =15
Debug: 1312 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar1 value 00000000, num =1
Debug: 1313 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar2 value 00000000, num =2
Debug: 1314 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar8 value 00000000, num =8
Debug: 1315 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar9 value 00000000, num =9
Debug: 1316 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar10 value 00000000, num =10
Debug: 1317 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar14 value 00000000, num =14
Debug: 1318 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar16 value 00000000, num =16
Debug: 1319 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar17 value 00000000, num =17
Debug: 1320 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar19 value 00000000, num =19
Debug: 1321 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar20 value 00000000, num =20
Debug: 1322 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar21 value 00000000, num =21
Debug: 1323 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar22 value 00000000, num =22
Debug: 1324 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar24 value 00000000, num =24
Debug: 1325 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar26 value 00000000, num =26
Debug: 1326 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar27 value 00000000, num =27
Debug: 1327 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar28 value 00000000, num =28
Debug: 1328 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar29 value 00000000, num =29
Debug: 1329 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar30 value 00000000, num =30
Debug: 1330 818 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar31 value 00000000, num =31
Debug: 1331 818 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1332 818 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0x400000
Debug: 1333 818 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1334 818 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x400925fc
Debug: 1335 818 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1336 818 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 1337 818 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1338 818 target.c:2206 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3ffc045c
Debug: 1339 818 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1340 818 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 1341 850 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1342 850 target.c:2206 target_free_working_area_restore(): freed 9724 bytes of working area at address 0x40090000
Debug: 1343 850 target.c:1986 print_wa_layout(): 0x40090000-0x40093fff (16384 bytes)
Debug: 1344 850 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1345 850 target.c:2206 target_free_working_area_restore(): freed 1116 bytes of working area at address 0x3ffc0000
Debug: 1346 850 target.c:1986 print_wa_layout(): 0x3ffc0000-0x3ffd7fff (98304 bytes)
Debug: 1347 850 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x30000 clear=0x600000
Debug: 1348 850 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=30000, state=2
Debug: 1349 850 esp_flash.c:344 esp_flash_get_size(): esp_flash_get_size size 0x400000
Info : 1350 850 esp_flash.c:1003 esp_flash_probe(): Auto-detected flash bank 'esp32.cpu1.flash' size 4096 KB
Info : 1351 850 esp_flash.c:1005 esp_flash_probe(): Using flash bank 'esp32.cpu1.flash' size 4096 KB
Debug: 1352 850 esp_flash.c:1022 esp_flash_probe(): allocated 1024 sectors
Debug: 1353 850 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 1354 865 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1355 865 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x0 clear=0x630000
Debug: 1356 865 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=0, state=2
Debug: 1357 865 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x40091994, 2 sections
Debug: 1358 865 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 9723, flags 1
Debug: 1359 865 target.c:2119 alloc_working_area_try_do(): allocated new working area of 9724 bytes at address 0x40090000
Debug: 1360 897 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1361 897 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1362 897 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 1363 897 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090000
Debug: 1364 897 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1365 897 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090200
Debug: 1366 897 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1367 897 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090400
Debug: 1368 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1369 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090600
Debug: 1370 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1371 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090800
Debug: 1372 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1373 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090a00
Debug: 1374 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1375 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090c00
Debug: 1376 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1377 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40090e00
Debug: 1378 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1379 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091000
Debug: 1380 912 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1381 912 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091200
Debug: 1382 929 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1383 929 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091400
Debug: 1384 929 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1385 929 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091600
Debug: 1386 929 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1387 929 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091800
Debug: 1388 929 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1389 929 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091a00
Debug: 1390 929 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1391 929 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091c00
Debug: 1392 929 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1393 929 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40091e00
Debug: 1394 944 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1395 944 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092000
Debug: 1396 944 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1397 944 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40092200
Debug: 1398 944 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1399 944 target.c:2471 target_write_buffer(): writing buffer of 507 byte at 0x40092400
Debug: 1400 944 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1401 944 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1402 944 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 1060, flags 0
Debug: 1403 944 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 1060 -> 1060
Debug: 1404 944 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 53 -> 56
Debug: 1405 944 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1116 bytes at address 0x3ffc0000
Debug: 1406 944 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1407 944 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1408 944 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 1409 944 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0000
Debug: 1410 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1411 960 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3ffc0200
Debug: 1412 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1413 960 target.c:2471 target_write_buffer(): writing buffer of 36 byte at 0x3ffc0400
Debug: 1414 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1415 960 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3ffc045c
Debug: 1416 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1417 960 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1418 960 target.c:1986 print_wa_layout(): b* 0x3ffc045c-0x3ffc085b (1024 bytes)
Debug: 1419 960 target.c:1986 print_wa_layout(): 0x3ffc085c-0x3ffd7fff (96164 bytes)
Debug: 1420 960 target.c:2119 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x400925fc
Debug: 1421 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1422 960 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1423 960 target.c:1986 print_wa_layout(): b* 0x400925fc-0x40092617 (28 bytes)
Debug: 1424 960 target.c:1986 print_wa_layout(): 0x40092618-0x40093fff (6632 bytes)
Debug: 1425 960 target.c:2471 target_write_buffer(): writing buffer of 28 byte at 0x400925fc
Debug: 1426 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1427 960 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 94.786 ms
Debug: 1428 960 xtensa_algorithm.c:114 xtensa_algo_init(): reg params count 9 (6/3).
Debug: 1429 960 xtensa_algorithm.c:61 xtensa_algo_regs_init_start(): Check stack addr 0x3ffc085c
Debug: 1430 960 xtensa_algorithm.c:64 xtensa_algo_regs_init_start(): Adjust stack addr to 0x3ffc0850
Debug: 1431 960 xtensa_algorithm.c:129 xtensa_algo_init(): Set arg[0] = 2 (a2)
Debug: 1432 960 xtensa_algorithm.c:140 xtensa_algo_init(): Set arg[1] = 4096 (a3)
Debug: 1433 960 xtensa_algorithm.c:140 xtensa_algo_init(): Set arg[2] = 61440 (a4)
Debug: 1434 960 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x400925fc, stack 1024 bytes @ 0x3ffc085c
Debug: 1435 960 xtensa.c:1267 xtensa_resume(): [esp32.cpu0] start
Debug: 1436 960 xtensa.c:1200 xtensa_prepare_resume(): [esp32.cpu0] current=0 address=0x400925fc, handle_breakpoints=1, debug_execution=1)
Debug: 1437 960 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 1438 960 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 400925FC
Debug: 1439 960 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowbase val 00000000
Debug: 1440 960 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg windowstart val 00000001
Debug: 1441 960 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 00060025
Debug: 1442 960 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 1443 960 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a0 value 00000000, num =1
Debug: 1444 960 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 3FFC0840, num =2
Debug: 1445 960 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a2 value 00000002, num =3
Debug: 1446 960 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00001000, num =4
Debug: 1447 960 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a4 value 0000F000, num =5
Debug: 1448 960 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 40091994, num =9
Debug: 1449 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1450 960 xtensa.c:1249 xtensa_do_resume(): [esp32.cpu0] start
Debug: 1451 960 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC01)
Debug: 1452 960 target.c:1860 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu0
Debug: 1453 960 esp32.c:508 esp32_handle_target_event(): 2
Debug: 1454 960 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 2
Debug: 1455 960 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 2
Debug: 1456 960 xtensa.c:2392 xtensa_handle_target_event(): 2
Debug: 1457 960 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 1458 960 target.c:3347 target_wait_state(): waiting for target halted...
Debug: 1459 1474 xtensa.c:934 xtensa_fetch_all_regs(): [esp32.cpu0] start
Debug: 1460 1474 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1461 1474 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1462 1474 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1463 1474 xtensa.c:1808 xtensa_poll(): [esp32.cpu0] Target halted, pc=0x40092612, debug_reason=00000001, oldstate=00000004
Debug: 1464 1474 xtensa.c:1812 xtensa_poll(): [esp32.cpu0] Halt reason=0x00000008, exc_cause=0, dsr=0x8080cc11
Info : 1465 1474 xtensa.c:1814 xtensa_poll(): [esp32.cpu0] Target halted, PC=0x40092612, debug_reason=00000001
Debug: 1466 1474 esp_xtensa_smp.c:258 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Debug: 1467 1474 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 1468 1474 esp_xtensa_smp.c:272 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 1469 1474 esp_xtensa_smp.c:317 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 1470 1474 target.c:1860 target_call_event_callbacks(): target event 17 (debug-halted) for core esp32.cpu0
Debug: 1471 1474 esp32.c:508 esp32_handle_target_event(): 17
Debug: 1472 1474 esp_xtensa_smp.c:608 esp_xtensa_smp_handle_target_event(): 17
Debug: 1473 1474 esp_xtensa.c:80 esp_xtensa_handle_target_event(): 17
Debug: 1474 1474 xtensa.c:2392 xtensa_handle_target_event(): 17
Debug: 1475 1474 xtensa.c:2170 xtensa_wait_algorithm(): Read mem params
Debug: 1476 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a15: 0x3ffc0294 -> 0x00000000
Debug: 1477 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a9: 0x3ffc0750 -> 0x00000000
Debug: 1478 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a8: 0x80092610 -> 0x00000000
Debug: 1479 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a4: 0x0000f000 -> 0x00000000
Debug: 1480 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a3: 0x00001000 -> 0x00000000
Debug: 1481 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register a1: 0x3ffc0840 -> 0x00000000
Debug: 1482 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ccount: 0x0134c188 -> 0x00000004
Debug: 1483 1474 xtensa.c:2194 xtensa_wait_algorithm(): Skip restoring register debugcause: 0x00000008 -> 0x00000020
Debug: 1484 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register eps6: 0x00060225 -> 0x0000001f
Debug: 1485 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register epc6: 0x40092612 -> 0x40000400
Debug: 1486 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register epc1: 0x40092566 -> 0x00000000
Debug: 1487 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ps: 0x00060225 -> 0x0000001f
Debug: 1488 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register configid0: 0x40092612 -> 0x40000400
Debug: 1489 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar63: 0x00000007 -> 0x00000000
Debug: 1490 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar61: 0x08000000 -> 0x00000000
Debug: 1491 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar59: 0x3ff42000 -> 0x00000000
Debug: 1492 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar58: 0x3ffc06c0 -> 0x00000000
Debug: 1493 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar57: 0x3ff42010 -> 0x00000000
Debug: 1494 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar51: 0x3ffc06c0 -> 0x00000000
Debug: 1495 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar49: 0x3ffc06a0 -> 0x00000000
Debug: 1496 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar48: 0x800622e8 -> 0x00000000
Debug: 1497 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar45: 0x08000000 -> 0x00000000
Debug: 1498 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar41: 0x3ffc06c0 -> 0x00000000
Debug: 1499 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar40: 0x80062d4d -> 0x00000000
Debug: 1500 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar39: 0x00000007 -> 0x00000000
Debug: 1501 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar37: 0x00200000 -> 0x00000000
Debug: 1502 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar36: 0x3ff42000 -> 0x00000000
Debug: 1503 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar35: 0x3ffae270 -> 0x00000000
Debug: 1504 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar34: 0x0134c104 -> 0x00000000
Debug: 1505 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar33: 0x3ffc0700 -> 0x00000000
Debug: 1506 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar32: 0x431bde83 -> 0x00000000
Debug: 1507 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar31: 0x00040000 -> 0x00000000
Debug: 1508 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar30: 0x00000010 -> 0x00000000
Debug: 1509 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar29: 0x0000000f -> 0x00000000
Debug: 1510 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar28: 0x00000010 -> 0x00000000
Debug: 1511 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar26: 0x00014956 -> 0x00000000
Debug: 1512 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar25: 0x3ffc0710 -> 0x00000000
Debug: 1513 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar24: 0x80091334 -> 0x00000000
Debug: 1514 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar23: 0x0000ffff -> 0x00000000
Debug: 1515 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar22: 0x00000100 -> 0x00000000
Debug: 1516 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar21: 0x00001000 -> 0x00000000
Debug: 1517 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar20: 0x00010000 -> 0x00000000
Debug: 1518 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar17: 0x3ffc0730 -> 0x00000000
Debug: 1519 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar16: 0x80091cee -> 0x00000000
Debug: 1520 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar15: 0x3ffc0294 -> 0x00000000
Debug: 1521 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar9: 0x3ffc0750 -> 0x00000000
Debug: 1522 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar8: 0x80092610 -> 0x00000000
Debug: 1523 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar4: 0x0000f000 -> 0x00000000
Debug: 1524 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar3: 0x00001000 -> 0x00000000
Debug: 1525 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register ar1: 0x3ffc0840 -> 0x00000000
Debug: 1526 1474 xtensa.c:2204 xtensa_wait_algorithm(): restoring register pc: 0x40092612 -> 0x40000400
Debug: 1527 1474 xtensa.c:572 xtensa_write_dirty_registers(): [esp32.cpu0] start
Debug: 1528 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg pc val 40000400
Debug: 1529 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg configid0 val 40000400
Debug: 1530 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ps val 0000001F
Debug: 1531 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg epc1 val 00000000
Debug: 1532 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg epc6 val 40000400
Debug: 1533 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg eps6 val 0000001F
Debug: 1534 1474 xtensa.c:585 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ccount val 00000004
Debug: 1535 1474 xtensa.c:701 xtensa_queue_write_dirty_user_regs_u32(): [esp32.cpu0] start
Debug: 1536 1474 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a1 value 00000000, num =2
Debug: 1537 1474 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a3 value 00000000, num =4
Debug: 1538 1474 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a4 value 00000000, num =5
Debug: 1539 1474 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a8 value 00000000, num =9
Debug: 1540 1474 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a9 value 00000000, num =10
Debug: 1541 1474 xtensa.c:650 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg a15 value 00000000, num =16
Debug: 1542 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar1 value 00000000, num =1
Debug: 1543 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar3 value 00000000, num =3
Debug: 1544 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar4 value 00000000, num =4
Debug: 1545 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar8 value 00000000, num =8
Debug: 1546 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar9 value 00000000, num =9
Debug: 1547 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar15 value 00000000, num =15
Debug: 1548 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar16 value 00000000, num =16
Debug: 1549 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar17 value 00000000, num =17
Debug: 1550 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar20 value 00000000, num =20
Debug: 1551 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar21 value 00000000, num =21
Debug: 1552 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar22 value 00000000, num =22
Debug: 1553 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar23 value 00000000, num =23
Debug: 1554 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar24 value 00000000, num =24
Debug: 1555 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar25 value 00000000, num =25
Debug: 1556 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar26 value 00000000, num =26
Debug: 1557 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar28 value 00000000, num =28
Debug: 1558 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar29 value 00000000, num =29
Debug: 1559 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar30 value 00000000, num =30
Debug: 1560 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar31 value 00000000, num =31
Debug: 1561 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar32 value 00000000, num =32
Debug: 1562 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar33 value 00000000, num =33
Debug: 1563 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar34 value 00000000, num =34
Debug: 1564 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar35 value 00000000, num =35
Debug: 1565 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar36 value 00000000, num =36
Debug: 1566 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar37 value 00000000, num =37
Debug: 1567 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar39 value 00000000, num =39
Debug: 1568 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar40 value 00000000, num =40
Debug: 1569 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar41 value 00000000, num =41
Debug: 1570 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar45 value 00000000, num =45
Debug: 1571 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar48 value 00000000, num =48
Debug: 1572 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar49 value 00000000, num =49
Debug: 1573 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar51 value 00000000, num =51
Debug: 1574 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar57 value 00000000, num =57
Debug: 1575 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar58 value 00000000, num =58
Debug: 1576 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar59 value 00000000, num =59
Debug: 1577 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar61 value 00000000, num =61
Debug: 1578 1474 xtensa.c:674 xtensa_write_dirty_registers(): [esp32.cpu0] Writing back reg ar63 value 00000000, num =63
Debug: 1579 1474 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1580 1474 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0x0
Debug: 1581 1474 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1582 1474 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x400925fc
Debug: 1583 1474 target.c:1986 print_wa_layout(): b* 0x40090000-0x400925fb (9724 bytes)
Debug: 1584 1474 target.c:1986 print_wa_layout(): 0x400925fc-0x40093fff (6660 bytes)
Debug: 1585 1491 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1586 1491 target.c:2206 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3ffc045c
Debug: 1587 1491 target.c:1986 print_wa_layout(): b* 0x3ffc0000-0x3ffc045b (1116 bytes)
Debug: 1588 1491 target.c:1986 print_wa_layout(): 0x3ffc045c-0x3ffd7fff (97188 bytes)
Debug: 1589 1538 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1590 1538 target.c:2206 target_free_working_area_restore(): freed 9724 bytes of working area at address 0x40090000
Debug: 1591 1538 target.c:1986 print_wa_layout(): 0x40090000-0x40093fff (16384 bytes)
Debug: 1592 1538 xtensa.c:833 xtensa_core_status_check(): [esp32.cpu0] DSR (8080CC11)
Debug: 1593 1538 target.c:2206 target_free_working_area_restore(): freed 1116 bytes of working area at address 0x3ffc0000
Debug: 1594 1538 target.c:1986 print_wa_layout(): 0x3ffc0000-0x3ffd7fff (98304 bytes)
Debug: 1595 1538 xtensa.c:776 xtensa_smpbreak_write(): [esp32.cpu0] write smpbreak set=0x30000 clear=0x600000
Debug: 1596 1538 xtensa.c:792 xtensa_smpbreak_set(): [esp32.cpu0] set smpbreak=30000, state=2
Info : 1597 1538 esp_flash.c:454 esp_flash_erase(): PROF: Erased 61440 bytes in 688.057 ms
Debug: 1598 1538 command.c:166 script_debug(): command - exit
Debug: 1599 1538 esp_xtensa.c:133 esp_xtensa_target_deinit(): start
Debug: 1600 1538 xtensa.c:2476 xtensa_target_deinit(): start
Debug: 1601 1538 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 1602 1538 target.c:1986 print_wa_layout(): 0x40090000-0x40093fff (16384 bytes)
Debug: 1603 1538 esp_xtensa.c:133 esp_xtensa_target_deinit(): start
Debug: 1604 1538 xtensa.c:2476 xtensa_target_deinit(): start
Debug: 1605 1538 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas

[gerekon]

Hi @skanky-dev !

Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED

This confusing error message can be printed on Windows, but it does not prevent debugger from working properly. So you just can ignore it.

Error: 940 507 esp_flash.c:382 esp_flash_get_mappings(): Failed to get flash maps (4294967290)!
Warn : Failed to get flash mappings (-4)!

4294967290 (-6 ) means ESP_STUB_ERR_INVALID_IMAGE. I think flasher returns this error because there are no valid app image in the flash at default factory app offset 0x10000. It is ok if app image has not been written yet to flash. This error can lead to the problems when you debugging application. For debugging applications located at non-default flash offset, please, see the docs.
But as far as I see you do not try to debug, just erase flash at offset 0x1000 and that was done successfully (see below). So looks like you have no any problems.

Using this on the command line: openocd -l openocd_log.txt -f board/esp32-wrover-kit-3.3v.cfg -c "init; reset halt; flash erase_address 0x1000 61440; exit"
Info : 1597 1538 esp_flash.c:454 esp_flash_erase(): PROF: Erased 61440 bytes in 688.057 ms

[skanky-dev]

Thank you very much. I'm not used to tools where errors in the output should be ignored and assumed this was the cause of what it turns out are unrelated issues being able to program and debug this project.
Where would I have been able to find this information about the Failed to get flash maps (4294967290) error as I could find nothing and posting on the esp and stackoverflow forums I didn't get any response either?
Also when you say "4294967290 (-6 )" do you mean "4294967290 (-4)" (was that a typo), just so I make sure I document ESP_STUB_ERR_INVALID_IMAGE correctly in my notes
Thanks

[gerekon]

Where would I have been able to find this information about the Failed to get flash maps (4294967290) error as I could find nothing and posting on the esp and stackoverflow forums I didn't get any response either?

Probably we need to convert it to warning to avoid confusion. @erhankur What do you think?

Also when you say "4294967290 (-6 )" do you mean "4294967290 (-4)" (was that a typo), just so I make sure I document ESP_STUB_ERR_INVALID_IMAGE correctly in my notes

If I am not wrong
4294967290 (unsigned int in dec) = 0xFFFFFFFA = -6 (signed int in dec)

[skanky-dev]

Ah OK, I thought it related to the "Warn : Failed to get flash mappings (-4)!" message after it. Thanks for clarifying

[erhankur]

Probably we need to convert it to warning to avoid confusion. @erhankur What do you think?

Yes, I agree. Actually, we were printing a warning message but looks like it is broken now. Will be fixed in one of the upcoming commits.

[Lsitar]

Hi, I also had these errors recently.
Espressif IDE 2.7.0, Win10, ESP32-S3, using built-in USB for JTAG and terminal simultaneously.

Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED

I fixed this by replacing USB driver. The ones installed by idf-env and Zadig weren't working, just UsbDriverTool worked for me. I set on Interface 0 "USB Serial Device".
On Interface 2 "USB JTAG/serial debug unit ", but there are several drivers available with this name, it must be the one that is visible in Device Manager in category "Universal Serial Bus devices" and not in "Ports (COM & LPT)".

Error: Failed to get flash maps (4294967290)

It was due to wrong setting "Partition Table -> Offset of partition table" in sdkconfig. Changing to default 0x8000 helped.