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Congratulations, you just finished the first stage of the Chisel Learning Journey provided by Intensivate.

Those of you who are on the Learning Journey for the first time, those who just read the theory intro and are supposed to learn the syntax now, you will be redirected to an address outside of this Wiki.

Before you do go to that second stage (explained in the next paragraph), please note somewhere that (maybe just bookmark this page), once you complete the work there, you are supposed to come back to this Wiki page for the third stage.

Great people at UC Berkeley have developed (and are keeping it up to date) the Chisel Bootcamp <== that is a Jupyter notebook that allows real time and interactive way of learning Chisel inline - while reading the explanations. Why we made you learn the explanations here? Well, two reasons: a) because we've added our own personal experiences gathered while developing a multicore server processor, and b) because we address some of the questions experienced Verilog hardware developers have raised earlier, most importantly, we discuss pros and cons of working with Chisel. Both of these, we believe, are important pieces of the puzzle. One last thing before you go: for this Learning Journey, you should do the cloud-based Chisel Bootcamp up to Chapter 3 <== that completes the second stage, and you should move on to the third stage. Here is the link, good luck and see you soon.

The Advanced Examples page is a work in progress, that covers advanced coding styles used in Rocket Chip

In the meantime, please consider advancing your knowledge through:

• Chisel3 Tutorial Wiki
• freechipsproject Chisel3 Wiki
• Generator Bootcamp
• Chisel3 Home Repo
• Chisel3 Tutorial

Concrete and more advanced examples may be found at:

• RISCV-Sodor cores
• A Simple As Possible RISCV-32I core with debug module
• Rocket Core
• LowRISC

Please take some time to provide feedback at our User Experiences page.

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