Mix in the MMIO Peripheral

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Mix in the MMIO Peripheral to Rocket-chip

We are done with the design of the peripheral, we now have to tell the host, Rocket-chip and the rocket core, that this peripheral exists and create the configuration to include it in the next binary simulator we are going to build. To do that, we need to edit two files.

First, open DigitalTop.scala and add this line to to the first block:

with chipyard.example.CanHavePeripheryJustRead

and this line to the second block of code:

with chipyard.example.CanHavePeripheryJustReadModuleImp

so that the DigitalTop.scala looks like this:

class DigitalTop(implicit p: Parameters) extends System
  with testchipip.CanHaveTraceIO
	// a dozen lines omitted
  with nvidia.blocks.dla.CanHavePeripheryNVDLA
  with chipyard.example.CanHavePeripheryJustRead
{
  override lazy val module = new DigitalTopModule(this)
}

class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
  with testchipip.CanHaveTraceIOModuleImp
 	// a dozen lines omitted
  with chipyard.example.CanHavePeripheryGCDModuleImp
  with freechips.rocketchip.util.DontTouch
  with chipyard.example.CanHavePeripheryJustReadModuleImp

Second, to create the Rocket-chip configuration open RocketConfigs.scala and add this block of code somewhere:

class JustReadTLRocketConfig extends Config(
  new chipyard.iobinders.WithUARTAdapter ++
  new chipyard.iobinders.WithTieOffInterrupts ++
  new chipyard.iobinders.WithBlackBoxSimMem ++
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithL2TLBs(1024) ++
  new chipyard.example.WithJustRead ++ // Use our MMIO peripheral, connect TL
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
  new freechips.rocketchip.subsystem.WithNoSlavePort ++
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

Save All, lock and load. Let’s see how all that hums together in the next page.

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