MMIO Chisel Module
Now it’s time to do the actual task of a front-end digital designer – write some RTL. We do that in a class that extends Chisel Module and, hance, its name ends with ChiselModule. This is where the actual implementation of the digital circuit we are designing is living. The class has to be parameterized in order to be consistent with the above Params class.
Inclusion of the HasJustReadIO mixin using the with keyword is an elegant way to get the io bundle in; this is equivalent to using extends, i.e. inheritance relation. The rest of the class body, related to concepts such as val, RegInit, := operator, etc. are basic Chisel, so refer to the first pages of the Learning Journey to get that explained.
class JustReadMMIOChiselModule(val w: Int) extends Module
with HasJustReadIO {
val a = RegInit(230.U(w.W))
io.toBeRead := a
}
Here you can learn more about good coding practices on registers in Chisel.
Basically, all this digital circuit does is create a register that holds 230 value and puts that value to the only output port.
In Fig. MMIO.2 the items related to the digital circuit are painted blue and relation of instantiation is represented with the arrow. The two items of white background are non-hardware overhead, Parameters and Keys.
Fig. MMIO.2. Widget circuit code in blue