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AArch64 decoder: Add all GPR-touching instructions #4848

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derekbruening opened this issue Apr 14, 2021 · 2 comments
Open

AArch64 decoder: Add all GPR-touching instructions #4848

derekbruening opened this issue Apr 14, 2021 · 2 comments
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@MDevereau
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Component-IR Google-Affecting OpSys-AArch64 Priority-High

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@derekbruening
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Splitting sub-pieces off from the master issue #2626 on finishing the AArch64 decoder. This piece covers ensuring that all instructions with general purpose register operands are fully decoded and encoded. Xref the instruction lists here: #2626 (comment)
MDevereau added a commit that referenced this issue Apr 15, 2021
@MDevereau
i#4848 AArch64 decoder: Add FCVTZU instruction (#4846)
67de69f 
This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

Issue: #4848
AssadHashmi pushed a commit that referenced this issue Apr 15, 2021
@MDevereau
Add support for FCVTZU to DynamoRIO codec (#4846)
f8ecbce 
i#4848 AArch64 decoder: Add FCVTZU instruction (#4846)

This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

Issue: #4848
MDevereau added a commit that referenced this issue Apr 16, 2021
@MDevereau
i#4848 AArch64 Decoder: Add floating-point to integer conversion inst…
625563d 
…ructions

This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

for FCVTAS, FCVTNS, FCVTPS, FCVTPU, and FCVTZS.

Issue: #4848
MDevereau added a commit that referenced this issue Apr 16, 2021
@MDevereau
i#4848 AArch64 Decoder: Add FCVT instructions
58c5b25 
This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

for FCVTAS, FCVTNS, FCVTPS, FCVTPU, and FCVTZS.

Issue: #4848
@MDevereau MDevereau mentioned this issue Apr 16, 2021
Merged
MDevereau added a commit that referenced this issue Apr 19, 2021
@MDevereau
i#4848 AArch64 GPR Decode: Add FCVT instructions
7376f03 
This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

for FCVTAS, FCVTNS, FCVTPS, FCVTPU, and FCVTZS.

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Apr 19, 2021
@MDevereau
i#4848 AArch64 GPR Decode: Add FCVT instructions (#4855)
138bce7 
This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

for FCVTAS, FCVTNS, FCVTPS, FCVTPU, and FCVTZS.

Issue: #4848, #2626
AssadHashmi pushed a commit that referenced this issue Apr 19, 2021
@MDevereau
i#4848 AArch64 Decoder: Add FCVT instructions (#4855)
23715da 
This implements:
- Scalar floating-point
- Vector floating-point
- Scalar floating-point to GPR

for FCVTAS, FCVTNS, FCVTPS, FCVTPU, and FCVTZS.

Issue: #4848, #2626
AssadHashmi added a commit that referenced this issue Apr 19, 2021
@AssadHashmi
i#2626 Add #fbits fixed-point handling to AArch64 codec
288f7d3 
This patch adds scale and immh:immb bitfeld handling
for the #fbits value in the codec using the FCVTZU
instruction as a use-case.

Issues: #2626, #4848
@AssadHashmi AssadHashmi mentioned this issue Apr 19, 2021
Merged
AssadHashmi added a commit that referenced this issue Apr 19, 2021
@AssadHashmi
i#2626 Add #fbits fixed-point handling to AArch64 codec (#4860)
20cbcf7 
This patch adds scale and immh:immb bitfeld handling
for the #fbits value in the codec using the FCVTZU
instruction as a use-case.

Issues: #2626, #4848
AssadHashmi added a commit that referenced this issue Apr 21, 2021
@AssadHashmi
i#2626 AArch64 codec: add #fbits fixed-point handling (#4860)
221d581 
This patch adds scale and immh:immb bitfeld handling
for the #fbits value in the codec using the FCVTZU
instruction as a use-case.

Issues: #2626, #4848
MDevereau added a commit that referenced this issue Apr 22, 2021
@MDevereau
i#4848 AArch64 GPR Decode: Add FCVTZS fixed-point
902effd 
Add handling of:
- FCVTZS (scalar, fixed-point)
- FCVTZS (vector, fixed-point)(scalar)

Issue: #2626, #4848
@MDevereau MDevereau mentioned this issue Apr 22, 2021
Merged
MDevereau added a commit that referenced this issue Apr 22, 2021
@MDevereau
i#4848 AArch64 GPR Decode: Add FCVTZS fixed-point
3b77676 
Add handling of:
- FCVTZS (scalar, fixed-point)
- FCVTZS (vector, fixed-point)(scalar)

Issue: #2626, #4848
MDevereau added a commit that referenced this issue Apr 23, 2021
@MDevereau
i#4848 AArch64 GPR Decode: Add FCVTZS fixed-point (#4869)
b6e6619 
Add handling of:
- FCVTZS (scalar, fixed-point)
- FCVTZS (vector, fixed-point)(scalar)

Issue: #2626, #4848
MDevereau added a commit that referenced this issue Apr 23, 2021
@MDevereau
i#4848: AArch64 GPR Decode: Add UCVTF and SCVTF
41d15cb 
Add handling of:
- scalar, integer
- vector, integer
- scalar, fixed-point
- vector, fixed-point

for instructions UCVTF and SCVTF

Issue: #2626, #4848
@MDevereau MDevereau mentioned this issue Apr 23, 2021
Merged
AssadHashmi pushed a commit that referenced this issue Apr 23, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR Decode: Add UCVTF and SCVTF (#4873)
3b74882 
Add handling of:
- scalar, integer
- vector, integer
- scalar, fixed-point
- vector, fixed-point

for instructions UCVTF and SCVTF

Issue: #2626, #4848
@derekbruening
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I found it surprising how many GPR-touching instructions were/are missing from the decoder: those could cause subtle bugs and all kinds of application crashes or abnormalities. I recall that the xx opcodes were supposed to decode GPR slots and try to include GPR registers they touch to avoid such bugs -- has that held for all these SIMD opcodes?

From #4855 (comment)

$ disasm_a64 1e290000
llvm-mc:   1e290000 fcvtpu w0, s0
capstone:  1e290000 fcvtpu w0, s0
bfd:       1e290000 fcvtpu w0, s0
DynamoRIO: 1e290000 xx $0x1e290000 %x0 %x0 %x0 %x9 -> %x0 %x0 %x0 %x9
$ disasm_a64 1e2903ff
llvm-mc:   1e2903ff fcvtpu wzr, s31
capstone:  1e2903ff fcvtpu wzr, s31
bfd:       1e2903ff fcvtpu wzr, s31
DynamoRIO: 1e2903ff xx $0x1e2903ff %sp %sp %x0 %x9 -> %sp %sp %x0 %x9

Here we have wzr/sp and w0 indicated as both read and written which does remove (most/all?) causes of bugs.

MDevereau added a commit that referenced this issue Apr 27, 2021
@MDevereau
i#2626 AArch64 v8.0 Decode: Order dis-a64.txt alphabetically
bc92f31 
Ordering dis-a64.txt alphabetically by instruction name will make it
much easier to navigate and detect missing or erroneous tests.

Issue: #2626, #4847, #4848, #4849
@MDevereau MDevereau mentioned this issue Apr 27, 2021
Merged
AssadHashmi pushed a commit that referenced this issue Apr 27, 2021
@MDevereau
i#2626 AArch64 v8.0 Decode: Order dis-a64.txt alphabetically (#4882)
1640ffe 
Ordering dis-a64.txt alphabetically by instruction name will make it
much easier to navigate and detect missing or erroneous tests.

Issue: #2626, #4847, #4848, #4849
@derekbruening derekbruening mentioned this issue May 25, 2021
Open
MDevereau added a commit that referenced this issue May 25, 2021
@MDevereau
i#4848 AArch64 v8.0 GPR decode: Add FCVT- to codec
03b5e23 
Adds the following instructions to the codec with decoder tests
- FCVTAU, FCVTL, FCVTL2, FCVTMS, FCVTN, FCVTN2

Issue: #4848, #2626
@MDevereau MDevereau mentioned this issue May 25, 2021
Merged
MDevereau added a commit that referenced this issue Jun 1, 2021
@MDevereau
i#4848 AArch64 v8.0 GPR decode: Add FCVT- to codec (#4921)
090e56f 
Adds the following instructions to the codec with decoder tests
- FCVTAU, FCVTL, FCVTL2, FCVTMS, FCVTN, FCVTN2

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Jun 1, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR decode: Add DUP to codec
cb1c54d 
Adds DUP to the codec with decoder tests

Issue: #4848, #2626
@MDevereau MDevereau mentioned this issue Jun 1, 2021
Merged
MDevereau added a commit that referenced this issue Jun 1, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR decode: Add SMOV to codec
9dc2771 
Adds SMOV to the codec with decoder tests

Issue: #4848, #2626
@MDevereau MDevereau mentioned this issue Jun 1, 2021
Merged
MDevereau added a commit that referenced this issue Jun 1, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR Decode: Add mul, rev32, rev64 to codec
5c2f42b 
Add any missing variations of mul, rev32, rev64 with
decoding tests

Issue: #4848, #2626
@MDevereau MDevereau mentioned this issue Jun 1, 2021
Merged
MDevereau added a commit that referenced this issue Jun 2, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR decode: Add SMOV to codec (#4935)
135ac4b 
Add SMOV to the codec with decoder tests

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Jun 2, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR decode: Add DUP to codec (#4934)
fcae6a5 
Add DUP to the codec with decoder tests

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Jun 17, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR Decode: Add mul, rev32, rev64 to codec (#4936)
f5902af 
Add missing variations of mul, rev32, rev64 with
decoding tests

Issue: #4848, #2626
@AssadHashmi
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Missing opcodes that touch GPR's: 75 of 254 as at 17-06-21.

@MDevereau MDevereau mentioned this issue Jun 21, 2021
Merged
MDevereau added a commit that referenced this issue Jun 21, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR Decode: CLZ, NEG, ORR and MOV (#4959)
4cf49af 
Adds the following AArch64 v8.0 instructions to the codec:

    CLZ (vector)
    NEG (vector)
    NEG (vector, scalar)
    ORR (vector, immediate)
    MOV (vector, element) (INS alias)
    MOV (vector, from general) (INS alias)
    MOV (vector, scalar)
    MOV (vector, to general) (UMOV alias)

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Jun 22, 2021
@MDevereau
i#4848: AArch64 v8.0 GPR Decode: CLZ, NEG, ORR and MOV (#4959)
0d633f1 
Adds the following AArch64 v8.0 instructions to the codec:

    CLZ (vector)
    NEG (vector)
    NEG (vector, scalar)
    ORR (vector, immediate)
    MOV (vector, element) (INS alias)
    MOV (vector, from general) (INS alias)
    MOV (vector, scalar)
    MOV (vector, to general) (UMOV alias)

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Jul 9, 2021
@MDevereau
i#4848: AArch64 v8.2 Decode: FCVTMU FCVTNU SYSL CMLT
12706f6 
Adds FCVTMU FCVTNU SYSL CMLT to the codec.

Issue: #4848, #2626
@MDevereau MDevereau mentioned this issue Jul 9, 2021
Merged
MDevereau added a commit that referenced this issue Jul 12, 2021
@MDevereau
i#4848: AArch64 v8.2 Decode: FCVTMU FCVTNU SYSL CMLT (#5002)
a178866 
Adds FCVTMU FCVTNU SYSL and CMLT to the codec.

Issue: #4848, #2626
MDevereau added a commit that referenced this issue Jul 12, 2021
@MDevereau
i#4848: AArch64 v8.2 Decode: FCVTMU FCVTNU SYSL CMLT (#5002)
c180473 
Adds FCVTMU FCVTNU SYSL and CMLT to the codec.

Issue: #4848, #2626
sapostolakis pushed a commit that referenced this issue Jul 14, 2021
@MDevereau @sapostolakis
i#4848: AArch64 v8.2 Decode: FCVTMU FCVTNU SYSL CMLT (#5002)
130ace0 
Adds FCVTMU FCVTNU SYSL and CMLT to the codec.

Issue: #4848, #2626
@derekbruening derekbruening mentioned this issue Nov 18, 2022
Closed
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@derekbruening @AssadHashmi @MDevereau