RISC-V: Add NEORV32 SoC support #39162
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Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <[email protected]>
Add UART driver for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <[email protected]>
Add devicetree nodes for the NEORV32 UART devices. Signed-off-by: Henrik Brix Andersen <[email protected]>
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area: Boards
area: Devicetree
area: Devicetree Binding
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Hi, I've been trying to use the Tcl script located in setups/vivado/arty-a7-test-setup in the repository you've linked above to test this port on HW, but it seems to be referencing non-declared variables (such as $fileset_neorv32), and non-existing board part (at least on my Vivado 2020.2). Could you point me to a script that would allow me to build this setup? This would be also beneficial to add to the board documentation in Zephyr.
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Very cool! Kind of a tangential question, but if someone wanted to do all of this in a module, would it be possible? |
Add GPIO driver for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <[email protected]>
Add devicetree nodes for the NEORV32 GPIO device. The GPIO port is 64 bits wide, but Zephyr only supports up to 32 bit wide GPIO ports. The GPIO device is therefore handled as two Zephyr GPIO devices with a nexus devicetree node mapping pins 0 to 31 to the device handling the lower half, and pins 32 to 63 to the device handling the upper half. Signed-off-by: Henrik Brix Andersen <[email protected]>
Add a basic board definition for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <[email protected]>
Add basic GPIO API test configuration for the NEORV32. Signed-off-by: Henrik Brix Andersen <[email protected]>
The GPIO block of the NEORV32 contains fully independent inputs and outputs (inputN is fully independent of outputN). This scenario is not handled by the 1pin GPIO test case, so exclude the neorv32 for now. Signed-off-by: Henrik Brix Andersen <[email protected]>
Take ownership of all the neorv32 specific files (dts bindings, soc implementation, drivers, and board definition). Signed-off-by: Henrik Brix Andersen <[email protected]>
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Thank you 👍
As you are likely aware, Zephyr does support out-of-tree SoC, driver, and board implementations (see https://docs.zephyrproject.org/latest/application/index.html#custom-board-devicetree-and-soc-definitions). Support for this particular SoC piggybacks on the |
I have just submitted a PR against the NEORV32 project for fixing the With this PR in, I was able to synthesise and implement the upstream example design using Xilinx Vivado 2020.02 (note, however, that you will need to modify the NEORV32 settings in that design in order to meet the requirements for running Zephyr on the NEORV32. The requirements are documented in the submitted board documentation). I have also submitted a PR for hinting at installing board support files: The Zephyr board documentation refers to the excellent upstream documentation for instructions on how to synthesise, implement, and load the NEORV32 FPGA designs. Any questions or generic NEORV32 documentation fixes are better addressed there. |
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Hi @henrikbrixandersen ,
Very interesting. Just couple questions.
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@nandojve Was your request for changes addressed? |
This PR adds basic Zephyr support for the NEORV32 RISC-V SoC.
More information about the NEORV32 can be obtained here:
The implementation passes the full suite of applicable test cases and samples as selected by
twister.