update for latest chisel, remove toBool and chisel3.core.

[sequencer]

No description provided.

[colinschmidt]

We will need to test this with chipyard before merging.

[sequencer]

Thanks! This PR is subsequent to chipsalliance/chisel#1730.

[sequencer]

any update on this PR?

[sequencer]

I think it's safe to merge:
related to chipsalliance/chisel#1730 :

diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
index c86e92085..17829143b 100644
--- a/core/src/main/scala/chisel3/Bits.scala
+++ b/core/src/main/scala/chisel3/Bits.scala
@@ -29,15 +29,6 @@ private[chisel3] sealed trait ToBoolable extends Element {
 
   /** @group SourceInfoTransformMacro */
   def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool
-
-  /** Casts this $coll to a [[Bool]]
-    *
-    * @note The width must be known and equal to 1
-    */
-  final def toBool(): Bool = macro SourceInfoWhiteboxTransform.noArg
-
-  /** @group SourceInfoTransformMacro */
-  def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool
 }
 
 /** A data type for values represented by a single bitvector. This provides basic bitwise operations.
@@ -315,11 +306,6 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
   /** Returns the contents of this wire as a [[scala.collection.Seq]] of [[Bool]]. */
   final def toBools(): Seq[Bool] = macro SourceInfoTransform.noArg
 
-  /** @group SourceInfoTransformMacro */
-  @chiselRuntimeDeprecated
-  @deprecated("Use asBools instead", "3.2")
-  def do_toBools(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[Bool] = do_asBools
-
   /** Returns the contents of this wire as a [[scala.collection.Seq]] of [[Bool]]. */
   final def asBools(): Seq[Bool] = macro SourceInfoTransform.noArg
 
@@ -369,10 +355,6 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
     }
   }
 
-  @chiselRuntimeDeprecated
-  @deprecated("Use asBool instead", "3.2")
-  final def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = do_asBool
-

[colinschmidt]

@alonamid Is going to make the chipyard PR that incorporates this and the other deprecation fixes you've made recently.

[sequencer]

Hi @colinschmidt, can we get this in now? :)

[sequencer]

ping

[jerryz123]

@sequencer Were you going to open a Chipyard PR aggregating all your bumps?

[sequencer]

Sure :)

[davidbiancolin]

These are not RTL changing, the same changes have been made in multiple submodules, so i'm going to green light this as it helps with my chisel bump.

I will be making the aggregating bump in CY.