Skip to content

Commit

Permalink
Merge pull request #837 from ucb-bar/mar2021-esp-bump
Browse files Browse the repository at this point in the history
Bump esp-tools (March 2021)
  • Loading branch information
alonamid authored Jun 10, 2021
2 parents 946cad0 + 39956dd commit 4338ef8
Show file tree
Hide file tree
Showing 11 changed files with 14 additions and 10 deletions.
3 changes: 2 additions & 1 deletion .circleci/config.yml
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ version: 2.1
parameters:
tools-cache-version:
type: string
default: "v9"
default: "v10"

# default execution env.s
executors:
Expand Down Expand Up @@ -287,6 +287,7 @@ jobs:
executor: main-env
steps:
- run-tests:
tools-version: "esp-tools"
group-key: "group-accels"
project-key: "chipyard-sha3"
chipyard-streaming-fir-run-tests:
Expand Down
3 changes: 3 additions & 0 deletions .circleci/run-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,9 @@ case $1 in
$LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
;;
chipyard-sha3)
export RISCV=$LOCAL_ESP_DIR
export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib
export PATH=$RISCV/bin:$PATH
(cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
$LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv
;;
Expand Down
2 changes: 1 addition & 1 deletion toolchains/esp-tools/riscv-isa-sim
Submodule riscv-isa-sim updated 951 files
2 changes: 1 addition & 1 deletion toolchains/esp-tools/riscv-pk
2 changes: 1 addition & 1 deletion toolchains/esp-tools/riscv-tests
Submodule riscv-tests updated 78 files
+6 −1 benchmarks/Makefile
+1 −0 benchmarks/common/test.ld
+24 −10 benchmarks/pmp/pmp.c
+3 −3 debug/Makefile
+2 −1 debug/README.md
+369 −21 debug/gdbserver.py
+2 −0 debug/programs/debug.c
+73 −0 debug/programs/semihosting.c
+82 −0 debug/programs/semihosting.h
+159 −0 debug/programs/vectors.S
+39 −1 debug/targets.py
+2 −0 debug/targets/RISC-V/spike-1.cfg
+10 −3 debug/targets/RISC-V/spike-2-hwthread.cfg
+10 −6 debug/targets/RISC-V/spike-2.cfg
+0 −27 debug/targets/RISC-V/spike-rtos.cfg
+1 −0 debug/targets/RISC-V/spike32-2-hwthread.py
+0 −17 debug/targets/RISC-V/spike32-2-rtos.py
+2 −0 debug/targets/RISC-V/spike32.py
+1 −0 debug/targets/RISC-V/spike64-2-hwthread.py
+3 −0 debug/targets/RISC-V/spike64-2-rtos.py
+4 −1 debug/targets/RISC-V/spike64-2.py
+1 −0 debug/targets/RISC-V/spike64.py
+3 −0 debug/targets/SiFive/HiFiveUnleashed-flash.py
+1 −0 debug/targets/SiFive/HiFiveUnleashed.cfg
+3 −0 debug/targets/SiFive/HiFiveUnleashed.py
+37 −10 debug/testlib.py
+1 −1 env
+15 −2 isa/Makefile
+73 −0 isa/macros/scalar/test_macros.h
+0 −2 isa/rv32mi/Makefrag
+1 −0 isa/rv32mi/shamt.S
+0 −2 isa/rv32si/Makefrag
+0 −2 isa/rv32ua/Makefrag
+0 −2 isa/rv32uc/Makefrag
+0 −2 isa/rv32ud/Makefrag
+0 −2 isa/rv32uf/Makefrag
+0 −2 isa/rv32ui/Makefrag
+0 −2 isa/rv32um/Makefrag
+10 −0 isa/rv32uzfh/Makefrag
+7 −0 isa/rv32uzfh/fadd.S
+7 −0 isa/rv32uzfh/fclass.S
+7 −0 isa/rv32uzfh/fcmp.S
+7 −0 isa/rv32uzfh/fcvt.S
+7 −0 isa/rv32uzfh/fcvt_w.S
+7 −0 isa/rv32uzfh/fdiv.S
+7 −0 isa/rv32uzfh/fmadd.S
+7 −0 isa/rv32uzfh/fmin.S
+38 −0 isa/rv32uzfh/ldst.S
+7 −0 isa/rv32uzfh/move.S
+7 −0 isa/rv32uzfh/recoding.S
+0 −2 isa/rv64mi/Makefrag
+0 −18 isa/rv64mi/illegal.S
+1 −1 isa/rv64mi/mcsr.S
+0 −2 isa/rv64si/Makefrag
+1 −0 isa/rv64si/csr.S
+0 −2 isa/rv64ua/Makefrag
+14 −8 isa/rv64ua/lrsc.S
+0 −2 isa/rv64uc/Makefrag
+4 −0 isa/rv64ud/Makefrag
+13 −11 isa/rv64ud/structural.S
+4 −0 isa/rv64uf/Makefrag
+4 −0 isa/rv64ui/Makefrag
+4 −4 isa/rv64ui/fence_i.S
+4 −0 isa/rv64um/Makefrag
+3 −3 isa/rv64uv/Makefrag
+0 −0 isa/rv64uv/vsetvlh.S
+10 −0 isa/rv64uzfh/Makefrag
+44 −0 isa/rv64uzfh/fadd.S
+44 −0 isa/rv64uzfh/fclass.S
+37 −0 isa/rv64uzfh/fcmp.S
+49 −0 isa/rv64uzfh/fcvt.S
+104 −0 isa/rv64uzfh/fcvt_w.S
+41 −0 isa/rv64uzfh/fdiv.S
+45 −0 isa/rv64uzfh/fmadd.S
+54 −0 isa/rv64uzfh/fmin.S
+38 −0 isa/rv64uzfh/ldst.S
+58 −0 isa/rv64uzfh/move.S
+46 −0 isa/rv64uzfh/recoding.S
2 changes: 1 addition & 1 deletion toolchains/riscv-tools/riscv-gnu-toolchain
2 changes: 1 addition & 1 deletion toolchains/riscv-tools/riscv-isa-sim
2 changes: 1 addition & 1 deletion toolchains/riscv-tools/riscv-pk
2 changes: 1 addition & 1 deletion toolchains/riscv-tools/riscv-tests

0 comments on commit 4338ef8

Please sign in to comment.