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[rtl] add "cached access" infrastructure #359

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Jul 6, 2022
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[rtl] add "cached access" infrastructure #359

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15dabbf
[rtl] add "cached access" infrastructure
stnolting Jul 5, 2022
7d6314a
[changelog] add v1.7.3.4
stnolting Jul 5, 2022
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12

| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 05.07.2022 | 1.7.3.4 | add "infrastructure" for cached (burst) bus accesses; [#359](https://github.com/stnolting/neorv32/pull/359) |
| 01.07.2022 | 1.7.3.3 | minor rtl cleanups; [#357](https://github.com/stnolting/neorv32/pull/357) |
| 29.06.2022 | 1.7.3.2 | :test_tube: add experimental core complex wrapper for integration into the [**LiteX**](https://github.com/enjoy-digital/litex) SoC builder framework; [#353](https://github.com/stnolting/neorv32/pull/353) |
| 28.06.2022 | 1.7.3.1 | :bug: fix bug that caused permanent CPU stall if illegal load/store instruction; [#356](https://github.com/stnolting/neorv32/pull/356) |
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59 changes: 32 additions & 27 deletions rtl/core/neorv32_busswitch.vhd
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Expand Up @@ -49,36 +49,39 @@ entity neorv32_busswitch is
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- controller interface a --
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
ca_bus_err_o : out std_ulogic; -- bus transfer error
ca_bus_cached_i : in std_ulogic; -- set if cached transfer
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
ca_bus_err_o : out std_ulogic; -- bus transfer error
-- controller interface b --
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
cb_bus_err_o : out std_ulogic; -- bus transfer error
cb_bus_cached_i : in std_ulogic; -- set if cached transfer
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
cb_bus_err_o : out std_ulogic; -- bus transfer error
-- peripheral bus --
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
p_bus_err_i : in std_ulogic -- bus transfer error
p_bus_cached_o : out std_ulogic; -- set if cached transfer
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
p_bus_err_i : in std_ulogic -- bus transfer error
);
end neorv32_busswitch;

Expand Down Expand Up @@ -217,6 +220,8 @@ begin
ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;

p_bus_cached_o <= ca_bus_cached_i when (arbiter.bus_sel = '0') else cb_bus_cached_i;

p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
p_bus_we_o <= p_bus_we or arbiter.we_trig;
Expand Down
4 changes: 4 additions & 0 deletions rtl/core/neorv32_icache.vhd
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Expand Up @@ -61,6 +61,7 @@ entity neorv32_icache is
host_ack_o : out std_ulogic; -- bus transfer acknowledge
host_err_o : out std_ulogic; -- bus transfer error
-- peripheral bus interface --
bus_cached_o : out std_ulogic; -- set if cached (!) access in progress
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_re_o : out std_ulogic; -- read enable
Expand Down Expand Up @@ -280,6 +281,9 @@ begin
-- signal cache miss to CPU --
miss_o <= '1' when (ctrl.state = S_CACHE_MISS) else '0';

-- cache access in progress --
bus_cached_o <= '1' when (ctrl.state = S_BUS_DOWNLOAD_REQ) or (ctrl.state = S_BUS_DOWNLOAD_GET) else '0';


-- Cache Memory ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
Expand Down
102 changes: 53 additions & 49 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -68,7 +68,7 @@ package neorv32_package is
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070303"; -- NEORV32 version - no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070304"; -- NEORV32 version - no touchy!
constant archid_c : natural := 19; -- official RISC-V architecture ID - hands off!

-- Check if we're inside the Matrix -------------------------------------------------------
Expand Down Expand Up @@ -1501,6 +1501,7 @@ package neorv32_package is
host_ack_o : out std_ulogic; -- bus transfer acknowledge
host_err_o : out std_ulogic; -- bus transfer error
-- peripheral bus interface --
bus_cached_o : out std_ulogic; -- set if cached (!) access in progress
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_re_o : out std_ulogic; -- read enable
Expand All @@ -1518,36 +1519,39 @@ package neorv32_package is
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- controller interface a --
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
ca_bus_err_o : out std_ulogic; -- bus transfer error
ca_bus_cached_i : in std_ulogic; -- set if cached transfer
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
ca_bus_err_o : out std_ulogic; -- bus transfer error
-- controller interface b --
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
cb_bus_err_o : out std_ulogic; -- bus transfer error
cb_bus_cached_i : in std_ulogic; -- set if cached transfer
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
cb_bus_err_o : out std_ulogic; -- bus transfer error
-- peripheral bus --
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
p_bus_err_i : in std_ulogic -- bus transfer error
p_bus_cached_o : out std_ulogic; -- set if cached transfer
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
p_bus_err_i : in std_ulogic -- bus transfer error
);
end component;

Expand Down Expand Up @@ -2008,32 +2012,32 @@ package neorv32_package is
component neorv32_xip
port (
-- globals --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active
-- host access: control register access port --
ct_addr_i : in std_ulogic_vector(31 downto 0); -- address
ct_rden_i : in std_ulogic; -- read enable
ct_wren_i : in std_ulogic; -- write enable
ct_data_i : in std_ulogic_vector(31 downto 0); -- data in
ct_data_o : out std_ulogic_vector(31 downto 0); -- data out
ct_ack_o : out std_ulogic; -- transfer acknowledge
ct_addr_i : in std_ulogic_vector(31 downto 0); -- address
ct_rden_i : in std_ulogic; -- read enable
ct_wren_i : in std_ulogic; -- write enable
ct_data_i : in std_ulogic_vector(31 downto 0); -- data in
ct_data_o : out std_ulogic_vector(31 downto 0); -- data out
ct_ack_o : out std_ulogic; -- transfer acknowledge
-- host access: transparent SPI access port (read-only) --
acc_addr_i : in std_ulogic_vector(31 downto 0); -- address
acc_rden_i : in std_ulogic; -- read enable
acc_data_o : out std_ulogic_vector(31 downto 0); -- data out
acc_ack_o : out std_ulogic; -- transfer acknowledge
acc_addr_i : in std_ulogic_vector(31 downto 0); -- address
acc_rden_i : in std_ulogic; -- read enable
acc_data_o : out std_ulogic_vector(31 downto 0); -- data out
acc_ack_o : out std_ulogic; -- transfer acknowledge
-- status --
xip_en_o : out std_ulogic; -- XIP enable
xip_acc_o : out std_ulogic; -- pending XIP access
xip_page_o : out std_ulogic_vector(03 downto 0); -- XIP page
xip_en_o : out std_ulogic; -- XIP enable
xip_acc_o : out std_ulogic; -- pending XIP access
xip_page_o : out std_ulogic_vector(03 downto 0); -- XIP page
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- SPI device interface --
spi_csn_o : out std_ulogic; -- chip-select, low-active
spi_clk_o : out std_ulogic; -- serial clock
spi_data_i : in std_ulogic; -- device data output
spi_data_o : out std_ulogic -- controller data output
spi_csn_o : out std_ulogic; -- chip-select, low-active
spi_clk_o : out std_ulogic; -- serial clock
spi_data_i : in std_ulogic; -- device data output
spi_data_o : out std_ulogic -- controller data output
);
end component;

Expand Down
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