Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

⚠️ remove A ISA extension, add Zalrsc ISA extension #1047

Merged
merged 10 commits into from
Oct 3, 2024

Conversation

stnolting
Copy link
Owner

@stnolting stnolting commented Oct 3, 2024

Remove "atomic memory access" (A) ISA extension and add Zalrsc ISA extension since the core only supports reservation-set operations (load-reservate lr.w and store-conditional sc.w), but not atomic read-modify-write memory operations.

@stnolting stnolting added the risc-v compliance Modification to comply with official RISC-V specs. label Oct 3, 2024
@stnolting stnolting self-assigned this Oct 3, 2024
@stnolting stnolting marked this pull request as ready for review October 3, 2024 18:27
@stnolting stnolting changed the title ⚠️ remove A ISA extension, add Zalrsc ISA extension ⚠️ remove A ISA extension, add Zalrsc ISA extension Oct 3, 2024
@stnolting stnolting merged commit 5bdaec7 into main Oct 3, 2024
10 checks passed
@stnolting stnolting deleted the split_a_isa_extension branch October 3, 2024 18:42
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
risc-v compliance Modification to comply with official RISC-V specs.
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant