⚠️ remove A ISA extension, add Zalrsc ISA extension (#1047)

stnolting · Oct 3, 2024 · 5bdaec7 · 5bdaec7
2 parents 56c1c9e + c7b08cc
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 03.10.2024 | 1.10.5.2 | :warning: remove `A` ISA extensions; replaced by new `Zalrsc` ISA extension | [#1047](https://github.com/stnolting/neorv32/pull/1047) |
 | 02.10.2024 | 1.10.5.1 | :warning: rework CFU interface; reduce minimal latency of CFU instructions from 4 cycles to 3 cycles | [#1046](https://github.com/stnolting/neorv32/pull/1046) |
 | 01.10.2024 | [**:rocket:1.10.5**](https://github.com/stnolting/neorv32/releases/tag/v1.10.5) | **New release** | |
 | 30.09.2024 | 1.10.4.11 | :warning: split `B` ISA extensions into individual sub-extensions: `Zba`, `Zbb`, `Zbs` | [#1044](https://github.com/stnolting/neorv32/pull/1044) |

diff --git a/README.md b/README.md
@@ -104,11 +104,11 @@ setup according to your needs. Note that all of the following SoC modules are en
 `RV32`
 [[`I`](https://stnolting.github.io/neorv32/#_i_isa_extension)/[`E`](https://stnolting.github.io/neorv32/#_e_isa_extension)]
 [[`M`](https://stnolting.github.io/neorv32/#_m_isa_extension)]
-[[`A`](https://stnolting.github.io/neorv32/#_a_isa_extension)]
 [[`C`](https://stnolting.github.io/neorv32/#_c_isa_extension)]
 [[`B`](https://stnolting.github.io/neorv32/#_b_isa_extension)]
 [[`U`](https://stnolting.github.io/neorv32/#_u_isa_extension)]
 [[`X`](https://stnolting.github.io/neorv32/#_x_isa_extension)]
+[[`Zalrsc`](https://stnolting.github.io/neorv32/#_zalrsc_isa_extension)]
 [[`Zba`](https://stnolting.github.io/neorv32/#_zba_isa_extension)]
 [[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_isa_extension)]
 [[`Zbkb`](https://stnolting.github.io/neorv32/#_zbkb_isa_extension)]

diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc
@@ -49,13 +49,6 @@ will raise an exception to allow a _software-based_ emulation provided by the ap
 access can be **emulated** using the NEORV32 runtime environment. See section <<_application_context_handling>>
 for more information.
 
-.No Atomic Read-Modify-Write Operations
-[IMPORTANT]
-The NEORV32 <<_a_isa_extension>> only supports the load-reservate (LR) and store-conditional (SR) instructions.
-The remaining read-modify-write operations are not supported. However, these missing instructions can
-be emulated. The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write
-instructions that is based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
-
 
 <<<
 // ####################################################################################################################
@@ -335,7 +328,7 @@ is driven by the _accessed_ device or bus system (i.e. a processor-internal memo
 | `rw`    |     1 | Access direction (`0` = read, `1` = write)
 | `src`   |     1 | Access source (`0` = instruction fetch, `1` = load/store)
 | `priv`  |     1 | Set if privileged (M-mode) access
-| `rvso`  |     1 | Set if current access is a reservation-set operation (atomic `lr` or `sc` instruction)
+| `rvso`  |     1 | Set if current access is a reservation-set operation (`lr` or `sc` instruction, <<_zalrsc_isa_extension>>)
 | `fence` |     1 | Data/instruction fence operation; valid without `stb` being set
 |=======================
 
@@ -382,7 +375,7 @@ additional latency). However, _all_ bus signals (request and response) need to b
 :sectnums:
 ==== Atomic Accesses
 
-The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_a_isa_extension>> execute as standard
+The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_zalrsc_isa_extension>> execute as standard
 load/store bus transactions but with the `rvso` ("reservation set operation") signal being set. It is the task of the
 <<_reservation_set_controller>> to handle these LR/SC bus transactions accordingly. Note that these reservation set operations
 are intended for processor-internal usage only (i.e. the reservation state is not available for processor-external modules yet).
@@ -391,12 +384,6 @@ are intended for processor-internal usage only (i.e. the reservation state is no
 [NOTE]
 See section <<_address_space>> / <<_reservation_set_controller>> for more information.
 
-.Read-Modify-Write Operations
-[IMPORTANT]
-Read-modify-write operations (like an atomic swap / `amoswap.w`) are **not** supported yet. However, the NEORV32
-<<_core_libraries>> provide an emulation wrapper for those unsupported instructions that is
-based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
-
 The figure below shows three exemplary bus accesses (1 to 3 from left to right). The `req` signal record represents
 the CPU-side of the bus interface. For easier understanding the current state of the reservation set is added as `rvs_valid` signal.
 
@@ -417,6 +404,11 @@ image::bus_interface_atomic.png[700]
 [NOTE]
 The "normal" load data mechanism is used to return success/failure of the `sc.w` instruction to the CPU (via the LSB of `rsp.data`).
 
+.Cache Coherency
+[IMPORTANT]
+Atomic operations **always bypass** the CPU caches using direct/uncached accesses. Care must be taken
+to maintain data cache coherency (e.g. by using the `fence` instruction).
+
 
 <<<
 // ####################################################################################################################
@@ -432,14 +424,14 @@ This chapter gives a brief overview of all available ISA extensions.
 [options="header",grid="rows"]
 |=======================
 | Name | Description | <<_processor_top_entity_generics, Enabled by Generic>>
-| <<_a_isa_extension,`A`>>               | Atomic memory access instructions                             | `RISCV_ISA_A`
 | <<_b_isa_extension,`B`>>               | Bit manipulation instructions                                 | _Implicitly_ enabled
 | <<_c_isa_extension,`C`>>               | Compressed (16-bit) instructions                              | `RISCV_ISA_C`
 | <<_e_isa_extension,`E`>>               | Embedded CPU extension (reduced register file size)           | `RISCV_ISA_E`
 | <<_i_isa_extension,`I`>>               | Integer base ISA                                              | Enabled if `RISCV_ISA_E` is **not** enabled
 | <<_m_isa_extension,`M`>>               | Integer multiplication and division instructions              | `RISCV_ISA_M`
 | <<_u_isa_extension,`U`>>               | Less-privileged _user_ mode extension                         | `RISCV_ISA_U`
 | <<_x_isa_extension,`X`>>               | Platform-specific / NEORV32-specific extension                | Always enabled
+| <<_zalrsc_isa_extension,`Zalrsc`>>     | Atomic reservation-set instructions                           | `RISCV_ISA_Zalrsc`
 | <<_zba_isa_extension,`Zba`>>           | Shifted-add bit manipulation instructions                     | `RISCV_ISA_Zba`
 | <<_zbb_isa_extension,`Zbb`>>           | Basic bit manipulation instructions                           | `RISCV_ISA_Zbb`
 | <<_zbkb_isa_extension,`Zbkb`>>         | Scalar cryptographic bit manipulation instructions            | `RISCV_ISA_Zbkb`
@@ -486,56 +478,6 @@ To benchmark a certain processor configuration for its setup-specific CPI value
 `sw/example/performance_tests` test programs.
 
 
-==== `A` ISA Extension
-
-The `A` ISA extension adds instructions and mechanisms for atomic memory access operations. Note that the NEORV32 `A`
-only includes the _load-reservate_ (`lr.w`) and _store-conditional_ (`sc.w`) instructions - the remaining read-modify-write
-instructions (like `amoswap`) are **not supported**. However, these missing instructions can be emulated using the
-LR and SC operations (quote from the RISC-V spec.: "_Any AMO can be emulated by an LR/SC pair._").
-
-.AMO Emulation
-[NOTE]
-The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write instructions that is
-based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
-
-Atomic instructions allow to notify an application if a certain memory location has been altered by another instance
-(like another process running on the same CPU or a DMA access). Hence, they can be used to implement synchronization
-mechanisms like mutexes and semaphores).
-
-The NEORV32 `A` extension is enabled via the `RISCV_ISA_A` generic (see <<_processor_top_entity_generics>>).
-When enabled the following additional instructions are available.
-
-.Instructions and Timing
-[cols="<2,<4,<3"]
-[options="header", grid="rows"]
-|=======================
-| Class | Instructions | Execution cycles
-| Load-reservate word    | `lr.w` | 5
-| Store-conditional word | `sc.w` | 5
-|=======================
-
-The `lr.w` instructions stores one word to a word-aligned address and registers a _reservation set_. The `sc.w`
-instruction stores a word to a word-aligned address only if the reservation set is still valid. Furthermore, the
-`sc.w` operations returns the state of the reservation set (0 = reservation set still valid, data has been written;
-1 = reservation set was broken, no data has been written). The reservation set is invalidated if another `lr.w` instruction
-is executed or if any write access to the _reservated_ address takes place. Traps and/or CPU privilege level changes
-do not modify current reservation sets.
-
-.`aq` and `rl` Bits
-[NOTE]
-The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all.
-
-.Atomic Memory Access on Hardware Level
-[NOTE]
-More information regarding the atomic memory accesses and the according reservation
-sets can be found in section <<_reservation_set_controller>>.
-
-.Cache Coherency
-[IMPORTANT]
-Atomic operations **always bypass** the CPU caches using direct/uncached accesses. Care must be taken
-to maintain data cache coherency (e.g. by using the `fence` instruction).
-
-
 ==== `B` ISA Extension
 
 The `B` ISA extension adds instructions for bit-manipulation operations.
@@ -657,6 +599,38 @@ RISC-V specs. Also, custom trap codes for <<_mcause>> are implemented.
 * There are <<_neorv32_specific_csrs>>.
 
 
+==== `Zalrsc` ISA Extension
+
+The `Zalrsc` ISA extension is a sub-extension of the RISC-V _atomic memory access_ (`A`) ISA extension and includes
+instructions for reservation-set operations (load-reservate `lr` and store-conditional `sc`) only.
+It is enabled by the top's `RISCV_ISA_Zalrsc` generic.
+
+.AMO / `A` Emulation
+[NOTE]
+The atomic memory access / read-modify-write operations of the `A` ISA extension can be emulated using the
+LR and SC operations (quote from the RISC-V spec.: "_Any AMO can be emulated by an LR/SC pair._").
+The NEORV32 <<_core_libraries>> provide an emulation wrapper for emulating AMO/read-modify-write instructions that is
+based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
+
+.Instructions and Timing
+[cols="<2,<4,<3"]
+[options="header", grid="rows"]
+|=======================
+| Class | Instructions | Execution cycles
+| Load-reservate word    | `lr.w` | 5
+| Store-conditional word | `sc.w` | 5
+|=======================
+
+.`aq` and `rl` Bits
+[NOTE]
+The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all.
+
+.Atomic Memory Access on Hardware Level
+[NOTE]
+More information regarding the atomic memory accesses and the according reservation
+sets can be found in section <<_reservation_set_controller>>.
+
+
 ==== `Zifencei` ISA Extension
 
 The `Zifencei` CPU extension allows manual synchronization of the instruction stream. This extension is always enabled.
@@ -1054,8 +1028,8 @@ behave like regular C functions but that evaluate to a single custom instruction
 .CFU Execution Time
 [NOTE]
 The actual CFU execution time depends on the logic being implemented. The CPU architecture requires a minimal execution
-time of 3 cycle and automatically terminates execution after 512 cycles if the CFU does not complete operation within
-this time window.
+time of 3 cycles (purely combinatorial CFU operation) and automatically terminates execution after 512 cycles if the CFU
+does not complete operation within this time window.
 
 .Instructions and Timing
 [cols="<2,<5,<2"]

diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc
@@ -220,7 +220,6 @@ will _not_ cause an illegal instruction exception.
 [options="header",grid="rows"]
 |=======================
 | Bit   | Name [C] | R/W | Function
-| 0     | `CSR_MISA_A_EXT` | r/- | **A**: CPU extension (atomic memory access) available, set when <<_a_isa_extension>> enabled
 | 1     | `CSR_MISA_B_EXT` | r/- | **B**: CPU extension (bit-manipulation) available, set when <<_b_isa_extension>> enabled
 | 2     | `CSR_MISA_C_EXT` | r/- | **C**: CPU extension (compressed instruction) available, set when <<_c_isa_extension>> enabled
 | 4     | `CSR_MISA_E_EXT` | r/- | **E**: CPU extension (embedded) available, set when <<_e_isa_extension>> enabled
@@ -972,7 +971,8 @@ discover ISA sub-extensions and CPU configuration options
 | 22    | `CSR_MXISA_ZBA`       | r/- | <<_zba_isa_extension>> available
 | 23    | `CSR_MXISA_ZBB`       | r/- | <<_zbb_isa_extension>> available
 | 24    | `CSR_MXISA_ZBS`       | r/- | <<_zbs_isa_extension>> available
-| 27:25 | -                     | r/- | _reserved_, hardwired to zero
+| 25    | `CSR_MXISA_ZALRSC`    | r/- | <<_zalrsc_isa_extension>> available
+| 27:26 | -                     | r/- | _reserved_, hardwired to zero
 | 28    | `CSR_MXISA_RFHWRST`   | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`)
 | 29    | `CSR_MXISA_FASTMUL`   | r/- | fast multiplication available when set (`FAST_MUL_EN`)
 | 30    | `CSR_MXISA_FASTSHIFT` | r/- | fast shifts available when set (`FAST_SHIFT_EN`)

diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -205,11 +205,11 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `ON_CHIP_DEBUGGER_EN`   | boolean   | false         | Implement the on-chip debugger and the CPU debug mode.
 | `DM_LEGACY_MODE`        | boolean   | false         | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
 4+^| **CPU <<_instruction_sets_and_extensions>>**
-| `RISCV_ISA_A`           | boolean   | false         | Enable <<_a_isa_extension>> (atomic memory accesses).
 | `RISCV_ISA_C`           | boolean   | false         | Enable <<_c_isa_extension>> (compressed instructions).
 | `RISCV_ISA_E`           | boolean   | false         | Enable <<_e_isa_extension>> (reduced register file size).
 | `RISCV_ISA_M`           | boolean   | false         | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division).
 | `RISCV_ISA_U`           | boolean   | false         | Enable <<_u_isa_extension>> (less-privileged user mode).
+| `RISCV_ISA_Zalrsc`      | boolean   | false         | Enable <<_zalrsc_isa_extension>> (atomic reservation-set operations).
 | `RISCV_ISA_Zba`         | boolean   | false         | Enable <<_zba_isa_extension>> (shifted-add bit-manipulation instructions).
 | `RISCV_ISA_Zbb`         | boolean   | false         | Enable <<_zbb_isa_extension>> (basic bit-manipulation instructions).
 | `RISCV_ISA_Zbkb`        | boolean   | false         | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation instructions).

diff --git a/docs/figures/neorv32_processor.png b/docs/figures/neorv32_processor.png
diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -28,11 +28,11 @@ entity neorv32_cpu is
     DEBUG_PARK_ADDR     : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
     DEBUG_EXC_ADDR      : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
     -- RISC-V ISA Extensions --
-    RISCV_ISA_A         : boolean; -- implement atomic memory operations extension
     RISCV_ISA_C         : boolean; -- implement compressed extension
     RISCV_ISA_E         : boolean; -- implement embedded RF extension
     RISCV_ISA_M         : boolean; -- implement mul/div extension
     RISCV_ISA_U         : boolean; -- implement user mode extension
+    RISCV_ISA_Zalrsc    : boolean; -- implement atomic reservation-set extension
     RISCV_ISA_Zba       : boolean; -- implement shifted-add bit-manipulation extension
     RISCV_ISA_Zbb       : boolean; -- implement basic bit-manipulation extension
     RISCV_ISA_Zbkb      : boolean; -- implement bit-manipulation instructions for cryptography
@@ -135,12 +135,12 @@ begin
   -- CPU ISA configuration (in alphabetical order - not in canonical order!) --
   assert false report "[NEORV32] CPU ISA: rv32" &
     cond_sel_string_f(RISCV_ISA_E,      "e",         "i") &
-    cond_sel_string_f(RISCV_ISA_A,      "a",         "" ) &
     cond_sel_string_f(riscv_b_c,        "b",         "" ) &
     cond_sel_string_f(RISCV_ISA_C,      "c",         "" ) &
     cond_sel_string_f(RISCV_ISA_M,      "m",         "" ) &
     cond_sel_string_f(RISCV_ISA_U,      "u",         "" ) &
     cond_sel_string_f(true,             "x",         "" ) & -- always enabled
+    cond_sel_string_f(RISCV_ISA_Zalrsc, "_zalrsc",   "" ) &
     cond_sel_string_f(RISCV_ISA_Zba,    "_zba",      "" ) &
     cond_sel_string_f(RISCV_ISA_Zbb,    "_zbb",      "" ) &
     cond_sel_string_f(RISCV_ISA_Zbkb,   "_zbkb",     "" ) &
@@ -190,12 +190,12 @@ begin
     DEBUG_PARK_ADDR  => DEBUG_PARK_ADDR,  -- cpu debug mode parking loop entry address
     DEBUG_EXC_ADDR   => DEBUG_EXC_ADDR,   -- cpu debug mode exception entry address
     -- RISC-V ISA Extensions --
-    RISCV_ISA_A      => RISCV_ISA_A,      -- implement atomic memory operations extension
     RISCV_ISA_B      => riscv_b_c,        -- implement bit-manipulation extension
     RISCV_ISA_C      => RISCV_ISA_C,      -- implement compressed extension
     RISCV_ISA_E      => RISCV_ISA_E,      -- implement embedded RF extension
     RISCV_ISA_M      => RISCV_ISA_M,      -- implement mul/div extension
     RISCV_ISA_U      => RISCV_ISA_U,      -- implement user mode extension
+    RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- implement atomic reservation-set extension
     RISCV_ISA_Zba    => RISCV_ISA_Zba,    -- implement shifted-add bit-manipulation extension
     RISCV_ISA_Zbb    => RISCV_ISA_Zbb,    -- implement basic bit-manipulation extension
     RISCV_ISA_Zbkb   => RISCV_ISA_Zbkb,   -- implement bit-manipulation instructions for cryptography
@@ -351,7 +351,7 @@ begin
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_lsu_inst: entity neorv32.neorv32_cpu_lsu
   generic map (
-    AMO_LRSC_ENABLE => RISCV_ISA_A -- enable atomic LR/SC operations
+    AMO_LRSC_ENABLE => RISCV_ISA_Zalrsc -- enable atomic LR/SC operations
   )
   port map (
     -- global control --