Merge pull request #1125 from slaclab/pre-release

Release Candidate v2.45.3
slaclab · Nov 3, 2023 · cede45e · cede45e
2 parents d92f7c4 + 850db38
commit cede45e
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Showing 4 changed files with 50 additions and 11 deletions.
diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd
@@ -56,6 +56,7 @@ architecture mapping of Pgp4TxLiteWrapper is
 
    signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
    signal pgpTxSlave  : AxiStreamSlaveType;
+   signal rstL        : sl;
 
 begin
 
@@ -87,13 +88,15 @@ begin
          locRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C,
          locRxLinkReady  => '1',
          remRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C,
-         remRxLinkReady  => '1',       
+         remRxLinkReady  => '1',
          -- PHY interface
-         phyTxActive     => '1',
+         phyTxActive     => rstL,
          phyTxReady      => phyTxReady,
          phyTxValid      => phyTxValid,
          phyTxStart      => open,
          phyTxData       => phyTxData(63 downto 0),
          phyTxHeader     => phyTxData(65 downto 64));
 
+   rstL <= not(rst);
+
 end architecture mapping;
diff --git a/python/surf/devices/ti/_Lmx2594.py b/python/surf/devices/ti/_Lmx2594.py
@@ -227,18 +227,19 @@ def addLinkVariable(name, description, offset, bitSize, mode, bitOffset=0, pollI
         @self.command(description='Load the CodeLoader .HEX file',value='',)
         def LoadCodeLoaderHexFile(arg):
 
+            self.DataBlock.set(value=0x2410,index=0, write=True) # MUXOUT_LD_SEL=readback
+
             ##################################################################
             # For the most reliable programming, TI recommends this procedure:
             ##################################################################
 
             # 1. Apply power to device.
-            reg = self.DataBlock.get(index=0, read=True)
 
             # 2. Program RESET = 1 to reset registers.
-            self.DataBlock.set(value=(reg|0x2), index=0, write=True)
+            self.DataBlock.set(value=0x2412, index=0, write=True)
 
             # 3. Program RESET = 0 to remove reset.
-            self.DataBlock.set(value=(reg&0xFFFD), index=0, write=True)
+            self.DataBlock.set(value=0x2410, index=0, write=True)
 
             # 4. Program registers as shown in the register map in REVERSE order from highest to lowest.
             with open(arg, 'r') as ifd:
@@ -250,10 +251,9 @@ def LoadCodeLoaderHexFile(arg):
                     # print( f'addr={addr}, data={hex(data)}' )
                     self.DataBlock.set(value=data, index=addr, write=True)
 
-            self.DataBlock.set(value=data, index=addr, write=True)
-
             # 5. Wait 10 ms.
             time.sleep(0.1)
 
             # 6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a stable state.
-            self.DataBlock.set(value=(data|0x8), index=0, write=True)
+            self.DataBlock.set(value=data&0xFFFB, index=addr, write=True)
+            time.sleep(0.1)
diff --git a/python/surf/xilinx/_RfDataConverter.py b/python/surf/xilinx/_RfDataConverter.py
@@ -125,6 +125,42 @@ def __init__(
                     expand  = False,
                 ))
 
+        for i in range(2):
+            self.add(pr.RemoteVariable(
+                name         = f'MtsFifoCtrl[{i}]',
+                description  = 'index[0] is MtsFifoCtrlADC, index[1] is MtsFifoCtrlDAC',
+                offset       =  0x0010+4*i,
+                bitSize      =  2,
+                bitOffset    =  0,
+                mode         = 'RW',
+                hidden       = True,
+            ))
+
+        self.add(pr.RemoteVariable(
+            name         = 'MtsSysRefEnable',
+            offset       =  0x6000+0x1C00+(0x24<<2), # XRFDC_DAC_TILE_DRP_ADDR(0) + XRFDC_HSCOM_ADDR offsets + XRFDC_MTS_SRCAP_T1
+            bitSize      =  1,
+            bitOffset    =  10, #  XRFDC_MTS_SRCAP_EN_TRX_M=0x0400
+            mode         = 'RW',
+            hidden       = True,
+        ))
+
+    def MtsAdcSync(self):
+        # Disable the FIFOs
+        self.MtsFifoCtrl[0].set(0x2)
+        # Enable SysRef Rx
+        self.MtsSysRefEnable.set(1)
+        # Disable the FIFOs
+        self.MtsFifoCtrl[0].set(0x3)
+
+    def MtsDacSync(self):
+        # Disable the FIFOs
+        self.MtsFifoCtrl[1].set(0x2)
+        # Enable SysRef Rx
+        self.MtsSysRefEnable.set(1)
+        # Disable the FIFOs
+        self.MtsFifoCtrl[1].set(0x3)
+
     def Init(self, dynamicNco=False):
 
         # Useful pointers

diff --git a/python/surf/xilinx/_RfTile.py b/python/surf/xilinx/_RfTile.py
@@ -59,7 +59,7 @@ def __init__(
             name         = 'RestartStateEnd',
             description  = 'End state for power-on sequence',
             offset       =  0x0008,
-            bitSize      =  8,
+            bitSize      =  4,
             bitOffset    =  0,
             mode         = 'RW',
             enum         = powerOnSequenceSteps,
@@ -69,7 +69,7 @@ def __init__(
             name         = 'RestartStateStart',
             description  = 'Start state for power-on sequence',
             offset       =  0x0008,
-            bitSize      =  8,
+            bitSize      =  4,
             bitOffset    =  8,
             mode         = 'RW',
             enum         = powerOnSequenceSteps,
@@ -79,7 +79,7 @@ def __init__(
             name         = 'CurrentState',
             description  = 'Current state register',
             offset       =  0x000C,
-            bitSize      =  8,
+            bitSize      =  4,
             bitOffset    =  0,
             mode         = 'RO',
             pollInterval = 1,