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i2s: Fix 2 issues. #6
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waveletboy
commented
Nov 21, 2018
- WS = 0, Left Channel; WS = 1, Right Channel
- Data start and end at falling edge of SCK
1. WS = 0, Left Channel; WS = 1, Right Channel 2. Data start and end at falling edge of SCK
Looks good, thanks! Merged in c78c8f6. |
Oh, forgot to mention: I've also updated the sigrok-test repo to match the new decoder output. If you have any additional i2c example files (*.sr) for our sigrok-dumps repo, that would also be great (for greater test-coverage). |
I have a 16bit 48khz I2S sample. Will upload once I have time. The other thing I noticed is that the I2S sample 2ch-16bit-16khz.sr is actually 32bit 8khz. |
Hi, did you get a chance to grab another i2s *.sr file for our sigrok-dumps repo btw? |
Hi Uwe, please see sigrokproject/sigrok-dumps#15
…On Sat, Mar 9, 2019 at 1:42 PM Uwe Hermann ***@***.***> wrote:
Hi, did you get a chance to grab another i2s *.sr file for our
sigrok-dumps repo btw?
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Hi Uwe,
I just closed #15 and created new one
sigrokproject/sigrok-dumps#16 which has better
samples.
…On Thu, Mar 19, 2020 at 2:42 PM Weixiao Zhang ***@***.***> wrote:
Hi Uwe, please see sigrokproject/sigrok-dumps#15
On Sat, Mar 9, 2019 at 1:42 PM Uwe Hermann ***@***.***>
wrote:
> Hi, did you get a chance to grab another i2s *.sr file for our
> sigrok-dumps repo btw?
>
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> You are receiving this because you authored the thread.
> Reply to this email directly, view it on GitHub
> <#6 (comment)>,
> or mute the thread
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