fix for chipsalliance/chisel#1730

sequencer · Apr 3, 2021 · 8b0df5e · 8b0df5e
1 parent 8392b28
commit 8b0df5e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala b/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala
@@ -141,7 +141,7 @@ object IOCell {
     * @param name An optional name or name prefix to use for naming IO cells
     * @return A Seq of all generated IO cell instances
     */
-  val toSyncReset:  (Reset) => Bool = _.toBool
+  val toSyncReset:  (Reset) => Bool = _.asBool
   val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
   def generateFromSignal[T <: Data, R <: Reset](
     coreSignal:        T,