Merge pull request #24 from KuthumiPepple/RVfpga-extended-resource

RVfpga extended resource

README.md

@@ -72,7 +72,8 @@ A collection of more advanced learning resources for RISC-V
 | Resource  |  Author(s) | Description  | Access | Date added |
 |---|---|---|---|---|
 | <span id="hardware-software-interface">**Computer Organization and Design RISC-V edition: The Hardware Software Interface (2nd edition)**</span> (good starting point)| David A. Patterson, John L. Hennesy | Covers the RISC-V Instruction Set in general and does an in-depth examination of the core RISC-V instructions. It also does a deep dive into RISC-V processor implementations. Each chapter includes real-world applications by tying concepts discussed with available modern computers. The book also highlights the interactions between hardware and software by continuously optimizing a sample software program based on the new hardware concepts introduced in each chapter.<br><br>*(Required background: knowledge of Logic design is needed to follow the contents of this book)* | <a href="https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128203315" target="_blank">[Amazon book link]</a>| 2024-01-10 |
-| <span id="computer-architecture-rvfpga">**Computer Architecture with an Industrial RISC-V Core [RVfpga]**</span> | Sarah Harris, Daniel Chaver-Martinez | This free EdX course expands on topics covered in **Digital Design and Computer Architecture, RISC-V edition** with hands-on learning. This course shows how to target a commercial RISC-V Core and RISC-V system-on-chip (SoC) to FPGA, program the RISC-V SoC, and add more functionalities to the RISC-V SoC | <a href="https://www.edx.org/learn/computer-programming/the-linux-foundation-computer-architecture-with-an-industrial-risc-v-core" target="_blank">[Edx course link]</a>| 2024-01-10 |
+| <span id="computer-architecture-rvfpga">**RVfpga: Computer Architecture with an Industrial RISC-V Core**</span> | Sarah Harris, Daniel Chaver-Martinez | This free EdX course expands on topics covered in **Digital Design and Computer Architecture, RISC-V edition** with hands-on learning. This course shows how to target a commercial RISC-V Core and RISC-V system-on-chip (SoC) to FPGA, program the RISC-V SoC, and add more functionalities to the RISC-V SoC | <a href="https://www.edx.org/learn/computer-programming/the-linux-foundation-computer-architecture-with-an-industrial-risc-v-core" target="_blank">[Edx course link]</a>| 2024-01-10 |
+| <span id="computer-architecture-rvfpga-extended">**RVfpga (extended): Understanding Computer Architecture**</span> | Sarah Harris, Daniel Chaver-Martinez | This is an updated and extended version of the free [edx course](#computer-architecture-rvfpga) above. The RVfpga Course in Computer Architecture provides hands-on understanding of a commercial RISC-V processor, RISC-V SoC, and the RISC-V ecosystem. Specifically, the RVfpga v3.0 course shows how to target a VeeR EL2 and a VeeR EH1 based system-on-chip (SoC) to 3 different FPGA boards: the Digilent Basys 3 board ($124 academic price), the Real Digital Boolean board ($74 academic price), and the Digilent Nexys A7 board ($262 academic price). The course can also be completed only in simulation; for that purpose, several simulation tools are provided which enable the user to simulate the system at different levels: from a Boolean/Nexys A7/Basys 3 virtual board down to the VeeR EH1/EL2 pipeline.<br><br>*(Required background: It is highly recommended to first read [Digital Design and Computer Architecture, RISC-V edition](#digital-design))* | [RVfpga v3.0 course link](https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/) | 2024-02-06 |
 |**learn-FPGA episode II: pipelining**|[BrunoLevy](https://github.com/BrunoLevy)|This tutorial explains how to transform the basic softcore from [episode I](#bruno-levy-episode-1) into an efficient pipelined processor. The tutorial follows a step-by-step approach, starting from a 5-states processor, transforming the states into stages, and solving data and control hazards by first observing what happens in real programs thanks to the included debugger/disassembler. Then it is explained how to gain more performance using register forwarding. Finally, branch prediction is introduced, from the simplest static branch prediction to more elaborate ones (gshare). The effect of the different optimizations are demonstrated using different codes (the classical dhrystones and coremark benchmarks, and a program that computes an image using raytracing).<br><br>*(Required background: It is highly recommended to read [episode I](#bruno-levy-episode-1) before episode II !)* | <a href="https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/PIPELINE.md" target="_blank">[GitHub]</a>| 2024-01-10 |
 | **Computer Architecture: A Quantitative Approach(6th edition)** | David A. Patterson, John L. Hennesy | Covers advanced computer architecture concepts pertaining to high performance computing principles and domain specific architectures along with examples and exercises pertaining to the RISC-V ISA-(6th Edition onwards). This is a step-up from the first book,(Hardware-Software Interface), with advanced concepts like Instruction , Data and Thread Level Parallelism along with introduction to Vector, SIMD and GPU architectures.It also continues the tradition of using real-world examples to demonstrate the concepts, by introducing memory organizations and architectures of ARM Cortex A8, Intel Core i7, Nvidia GTX-280 GPUs and so on.<br><br>*(Required Background: It is recommended that you first read the [Hardware Software Interface](#hardware-software-interface) before this book !)* | <a href="https://a.co/d/fuvp97D" target="_blank">[Amazon book link]</a>| 2024-01-10 |
 | **Tutorial: RISC-V Vector Extension Demystified** | Thang Tran | A very in-depth, three hour long video introduction to the RISC-V Vector extension. | <a href="https://youtu.be/oTaOd8qr53U" target="_blank">[Youtube video]</a> | 2024-01-10 |