Merge pull request #23 from ajithpv/main

Update author list to softwares and tools

README.md

@@ -82,13 +82,13 @@ A collection of more advanced learning resources for RISC-V
 #### Softwares and Tools
 A collection of tools that can be used along with the beginner or intermediate-level learning resources for a better understanding or visualization of the RISC-V ISA
 
-| Resource | Description  | Access | Date added |
-|---|---|---|---|
-| **emulsiV** | emulsiV is a visual simulator for a simple RISC processor called Virgule. Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program. | <a href="https://eseo-tech.github.io/emulsiV/" target="_blank">[website]</a> | 2023-20-12 |
-| **RISC-V Instruction Encoder/Decoder** | This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other. | <a href="https://luplab.gitlab.io/rvcodecjs/" target="_blank">[website]</a> | 2023-20-12 |
-| **CREATOR** | CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software. Only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required. | <a href="https://creatorsim.github.io/creator/" target="_blank">[website]</a> | 2023-20-12 |
-| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | <a href="https://github.com/cvut/qtrvsim/" target="_blank">[Github]</a> | 2023-20-12 |
-| **RVV intrinsics viewer** | A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search. This can be a useful resource when writing rvv code. | <a href="https://dzaima.github.io/intrinsics-viewer/" target="_blank">[website]</a> | 2023-20-12 |
+| Resource |  Author(s) | Description  | Access | Date added |
+|---|---|---|---|---|
+| **emulsiV** | Guillaume Savaton, ESEO | emulsiV is a visual simulator for a simple RISC processor called Virgule. Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program. | <a href="https://eseo-tech.github.io/emulsiV/" target="_blank">[website]</a> | 2023-20-12 |
+| **RISC-V Instruction Encoder/Decoder** | LupLab @ University of California, Davis | This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other. | <a href="https://luplab.gitlab.io/rvcodecjs/" target="_blank">[website]</a> | 2023-20-12 |
+| **CREATOR** | Diego Camarmas Alonso,Félix García Carballeira,Alejandro Calderón Mateos,Elías del Pozo Puñal | CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software. Only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required. | <a href="https://creatorsim.github.io/creator/" target="_blank">[website]</a> | 2023-20-12 |
+| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | Computer Architectures Education project at Czech Technical University | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | <a href="https://github.com/cvut/qtrvsim/" target="_blank">[Github]</a> | 2023-20-12 |
+| **RVV intrinsics viewer** | dzaima | A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search. This can be a useful resource when writing rvv code. | <a href="https://dzaima.github.io/intrinsics-viewer/" target="_blank">[website]</a> | 2023-20-12 |
 
 #### Open RISC-V Implementations
 A list of open RISC-V Implementations