ACTs for VM SV48

[HAMZA-AFZAL404]

Hello everyone,

This PR is adding a comprehensive set of self-checking assembly tests for the architectural verification of SV48. These tests are hand-written and follows the test plan provided in the following testplan. All the tests are RISCOF compliant. I have executed these tests using SAIL as our reference model and SPIKE as the Device Under Test (DUT).

Here's an overview of the different categories covered by these tests

Test Features	Test Description
PMP Permissions	Assesses PMP permissions on both physical addresses and PTEs.
PTE Validity and Permissions	Evaluates the Read/Write/Execute (RWX) permissions of PTEs with the valid bit set to 0, including reserved encodings at level3,level2, level1 and level0 PTEs, and non-leaf PTEs for level 0 in both user and supervisor modes.
Access on Supervisor and User Pages	Tests access permissions for Supervisor and User mode pages in both supervisor and user privilege level3,level2, level1 and level0 PTEs.
Executable Page Readability	Checks the behavior of readable executable pages with different s/mstatus.MXR set and unset.
RWX access on U mode pages in S mode	Examines RWX access of User mode pages in Supervisor mode with different s/mstatus.SUM set and unset.
Access and Dirty Bit Implementation	Evaluates the implementation and effects of the access and dirty bits (A and D) on page fault exceptions.
Misaligned Superpage	Investigates page faults for misaligned superpages at level3,level 2 and level 1 PTEs in both user and supervisor modes.

Enhancements to test_macros.h and arch_test.h

1. First and foremost, I've added the ALL_MEM_PMP macro, a significant addition that grants PMP (Physical Memory Protection) permissions to all available memory regions and is particularly useful whenever we want to grant PMP permissions to all regions.
2. Additionally, I've introduced the PTE_SETUP_RV64 macro, which marks a substantial improvement in memory page table management. Previously, we had the "PTE_SETUP_RV32" macro, exclusively designed for RV32 architecture. With this update, this macro now extends its support to RV64 architecture, allowing us to efficiently set up Page Table Entries for sv39, sv48 and sv57.
3. Furthermore, the SATP_SETUP_RV64 macro has been introduced to facilitate the setup of the SATP (Supervisor Address Translation and Protection) register's MODE field. This macro enhances support for virtualization across different modes in RV64 architecture, including sv39, sv48, and sv57.
4. Lastly, the SIGNATURE_AREA macro has been added. This macro plays a crucial role within our tests, ensuring that the save area aligns with the specific requirements of each test and facilitating the dumping of signatures as needed.

I've made modifications to arch_test.h by introducing new macro definitions. These macros are not only utilized within the newly added macros in test_macros.h but also find extensive use within the test cases themselves.

Important Note

These tests have been specifically designed for the RV64 architecture. However, it's important to note that by default, both SPIKE and SAIL do not support addresses greater than 32 bits. The physical address space for sv48 architecture extends up to 56 bits. To enable support for this 56-bit address space:

• For SPIKE, use the -m<size in MB> flag in the execute command within the riscof_spike.py script. In the context of a 56-bit address space, set the size to 8796093022208 MB, equivalent to 0x80000000000, effectively encompassing the entire 56-bit memory.
• For SAIL, utilize the --ram-size=<size in MB> flag in the execute command within the riscof_sail_cSim.py script, again setting the size to 8796093022208 MB.

Ensure that this size is configured as the starting address in our linker file to correctly map memory for these tests.

Related Issues

This PR is related to SV48 Vm ACTs, as discussed in Virtual Memory ACT

Ratified/Unratified Extensions

• Ratified
• Unratified

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports (See this for more info): < (Coverage-Report) >
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : < Adding the cover-points definition of the SV48 riscv-software-src/riscv-ctg#90 >
• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.