SV32-DV-Plan Execution

[HAMZA-AFZAL404]

Description

Hello everyone,
This PR is adding tests for the SV 32 virtual memory for the RISC-V privileged architecture. These tests are hand-written and follows the test plan provided in the following Google Sheets document. All the tests are RISCOF compliant. We have executed these tests using Sail as our reference model and Spike as the Device Under Test (DUT).Here's an overview of the different categories covered by these tests

Test Features	Test Description
SATP	Examines various common cases related to SATP, including access permissions at different privilege levels, the modes field, and ASIDLEN settings.
PMP Permissions	Assesses PMP permissions on both physical addresses and PTEs.
PTE Validity and Permissions	Evaluates the Read/Write/Execute (RWX) permissions of PTEs with the valid bit set to 0, including reserved encodings at level 1 and level 0 PTEs, and non-leaf PTEs for level 0 in both user and supervisor modes.
Access on Supervisor and User Pages	Tests access permissions for Supervisor and User mode pages in both supervisor and user privilege levels for both level 0 and level 1 PTEs.
Executable Page Readability	Checks the behavior of readable executable pages with different s/mstatus.MXR settings.
RWX access on U mode pages in S mode	Examines RWX access of User mode pages in Supervisor mode with different s/mstatus.SUM settings.
Access and Dirty Bit Implementation	Evaluates the implementation and effects of the access and dirty bits (A and D) on page fault exceptions.
Misaligned Superpage	Investigates page faults for misaligned superpages at level 1 PTEs in both user and supervisor modes.

Related Issues

NA

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[UmerShahidengr]

I would also like to mention that this project was started by @Abdulwadoodd who developed its basic testplan with the help of @allenjbaum, and it was also assigned to a few undergraduate students (@Masooma82, @uneeb125, @wajidali4907, @Abdullah-61) who developed some tests (available here). @HAMZA-AFZAL404 and co have also written tests of Virtual Memory for CVA6 which are running on core-v-verif and have been submitted here.
It was a long project completed by 10xEngineers and a few students of UET Lahore. So credit to all of them.

[UmerShahidengr]

New PR is available with the updated SV32 tests so closing this one out