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Added regenerated tests of divw and remw through riscv_ctg to solve corner case of issue#300 #365

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merged 2 commits into from
Oct 10, 2023

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alitariq4589
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@alitariq4589 alitariq4589 commented Jun 22, 2023

Description

In this PR, I have added the tests for a single corner case of divw and remw which involves dividing the most negative integer by -1 and expects an overflow in result. This corner case is stated in section 9.2 of riscv unprivilege specification.

Related Issues

#300

Ratified/Unratified Extensions

  • Ratified
  • Unratified

List Extensions

RV64IM

Reference Model Used

  • SAIL
  • Spike
  • Other - < SPECIFY HERE >

Mandatory Checklist:

  • All tests are compliant with the test-format spec present in this repo ?
  • Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
  • Ran the new tests on RISCOF in coverage mode
  • Link to Google-Drive folder containing the new coverage reports (See this for more info): link
  • Link to PR in RISCV-ISAC from which the reports were generated : RISC-V ISA Coverage Generator, version 0.17.0 (Installed from pip)
  • Changelog entry created with a minor patch

Optional Checklist:

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@allenjbaum allenjbaum left a comment

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Ugh - regenerating this entire test means you cannot see where you added this one case.
But: does this also handle the other cases that Stacy identified as missing coverage?

@UmerShahidengr
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Ugh - regenerating this entire test means you cannot see where you added this one case. But: does this also handle the other cases that Stacy identified as missing coverage?

Yes. These tests were generated via updated cgf file which include those missing coverpoints pointed by Stacy.

Signed-off-by: Ali Tariq  <[email protected]>
@alitariq4589
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Mandatory checklist has been completed. Regarding the coverage report, I was having some confusion which file to add in the zip file. So I have zipped complete riscof work folder. This should be good to go now.

@allenjbaum allenjbaum self-assigned this Oct 10, 2023
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I can see the missing case, so this is good to go.

@allenjbaum allenjbaum merged commit 751348f into riscv-non-isa:main Oct 10, 2023
@alitariq4589 alitariq4589 mentioned this pull request Oct 31, 2023
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3 participants