Fix ISA strings for Zcf, Zcd, and RV64 sra (#597)

* Fix RV64 sra check ISA regex * Fix Zcf and Zcd ISA strings
riscv-non-isa · Jan 16, 2025 · 2243dd4 · 2243dd4
1 parent 37e34be
commit 2243dd4
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Showing 13 changed files with 22 additions and 22 deletions.
diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fld)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fldsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_SIGBASE(x1,signature_x1_1)

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fsd)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFDC,RV64IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fsdsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFC")
+RVTEST_ISA("RV32IF_Zcf")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*C.*);def TEST_CASE_1=True;",c.fswsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fswsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IFDC")
+RVTEST_ISA("RV64IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fld)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IFDC")
+RVTEST_ISA("RV64IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fldsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_SIGBASE(x1,signature_x1_1)

diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IFDC")
+RVTEST_ISA("RV64IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fsd)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IFDC")
+RVTEST_ISA("RV64IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fsdsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/I/src/sra-01.S b/riscv-test-suite/rv64i_m/I/src/sra-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sra)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*);def TEST_CASE_1=True;",sra)
 
 RVTEST_SIGBASE(x1,signature_x1_1)