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[ACT] [CTG] [ISAC] Add support Zdinx extension (#499)
* Updated RV32Zdinx and RV64Zdinx test case * Updated Zdinx instruction support with respect to riscv-ctg and riscv-isac --------- Signed-off-by: anuani21 <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,188 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
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| fadd.d_b1: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b1(flen,64, "fadd.d", 2, True)': 0 | ||
|
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||
| fadd.d_b2: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b2(flen,64, "fadd.d", 2, True)': 0 | ||
|
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||
| fadd.d_b3: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b3(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b4: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b4(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b5: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b5(flen,64, "fadd.d", 2, True)': 0 | ||
|
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||
| fadd.d_b7: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b7(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b8: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b8(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b10: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b10(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b11: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b11(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b12: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b12(flen,64, "fadd.d", 2, True)': 0 | ||
|
|
||
| fadd.d_b13: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fadd.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rs2: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b13(flen,64, "fadd.d", 2, True)': 0 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
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| fclass.d_b1: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fclass.d: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b1(flen,64, "fclass.d", 1, True)': 0 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
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| fcvt.d.l_b25: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fcvt.d.l: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b25(flen,64, "fcvt.d.l", 1, True)': 0 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
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| fcvt.d.lu_b25: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fcvt.d.lu: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b25(flen,64, "fcvt.d.lu", 1, True)': 0 | ||
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||
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|
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,28 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
|
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||
| fcvt.d.w_b25: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fcvt.d.w: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b25(flen,32, "fcvt.d.w", 1, True)': 0 | ||
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| fcvt.d.w_b26: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) | ||
| mnemonics: | ||
| fcvt.d.w: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b26(32, "fcvt.d.w", 1, True)': 0 | ||
|
|
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,28 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
|
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| fcvt.d.wu_b25: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx) | ||
| mnemonics: | ||
| fcvt.d.wu: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b25(flen,32, "fcvt.d.wu", 1, True)': 0 | ||
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| fcvt.d.wu_b26: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zdinx) | ||
| mnemonics: | ||
| fcvt.d.wu: 0 | ||
| rs1: | ||
| <<: *pair_regs | ||
| rd: | ||
| <<: *pair_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b26(32, "fcvt.d.wu", 1, True)': 0 | ||
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