Merge pull request #791 from Silabs-ArjanB/ArjanB_clicf14

Updated CLIC to version 0.9-draft, 2/14/2023. Changed mintstatus CSR …

docs/user_manual/source/control_status_registers.rst

@@ -54,7 +54,7 @@ instruction exception.
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
   | 0x305         | ``mtvec``         | MRW       |                          | Machine Trap-Handler Base Address                       |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
-  | 0x307         | ``mtvt``          | MRW       | ``SMCLIC`` = 1           | Machine Trap-Handler Vector Table Base Address          |
+  | 0x307         | ``mtvt``          | MRW       | ``CLIC`` = 1             | Machine Trap-Handler Vector Table Base Address          |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
   | 0x310         | ``mstatush``      | MRW       |                          | Machine Status (upper 32 bits).                         |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
@@ -76,13 +76,13 @@ instruction exception.
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
   | 0x344         | ``mip``           | MRW       |                          | Machine Interrupt Pending Register                      |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
-  | 0x345         | ``mnxti``         | MRW       | ``SMCLIC`` = 1           | Interrupt handler address and enable modifier           |
+  | 0x345         | ``mnxti``         | MRW       | ``CLIC`` = 1             | Interrupt handler address and enable modifier           |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
-  | 0x347         | ``mintthresh``    | MRW       | ``SMCLIC`` = 1           | Interrupt-level threshold                               |
+  | 0x347         | ``mintthresh``    | MRW       | ``CLIC`` = 1             | Interrupt-level threshold                               |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
-  | 0x348         | ``mscratchcsw``   | MRW       | ``SMCLIC`` = 1           | Conditional scratch swap on priv mode change            |
+  | 0x348         | ``mscratchcsw``   | MRW       | ``CLIC`` = 1             | Conditional scratch swap on priv mode change            |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
-  | 0x349         | ``mscratchcswl``  | MRW       | ``SMCLIC`` = 1           | Conditional scratch swap on level change                |
+  | 0x349         | ``mscratchcswl``  | MRW       | ``CLIC`` = 1             | Conditional scratch swap on level change                |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
   | 0x7A0         | ``tselect``       | MRW       | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Select Register                                 |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
@@ -134,7 +134,7 @@ instruction exception.
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
   | 0xF15         | ``mconfigptr``    | MRO       |                          | Machine Configuration Pointer                           |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
-  | 0xF46         | ``mintstatus``    | MRO       | ``SMCLIC`` = 1           | Current interrupt levels                                |
+  | 0xFB1         | ``mintstatus``    | MRO       | ``CLIC`` = 1             | Current interrupt levels                                |
   +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
 
 .. table:: Control and Status Register Map (Unprivileged and User-Level CSRs)
@@ -580,8 +580,8 @@ All bitfields in the ``misa`` CSR read as 0 except for the following:
 
    None of the ``misa`` bits can be changed by writing the ``misa`` CSR.
 
-Machine Interrupt Enable Register (``mie``) - ``SMCLIC`` == 0
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Interrupt Enable Register (``mie``) - ``CLIC`` == 0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x304
 
@@ -625,8 +625,8 @@ Detailed:
   |  0          | WARL (0x0)| Reserved. Hardwired to 0.                                                                |
   +-------------+-----------+------------------------------------------------------------------------------------------+
 
-Machine Interrupt Enable Register (``mie``) - ``SMCLIC`` == 1
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Interrupt Enable Register (``mie``) - ``CLIC`` == 1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x304
 
@@ -649,8 +649,8 @@ Detailed:
 
 .. _csr-mtvec:
 
-Machine Trap-Vector Base Address (``mtvec``) - ``SMCLIC`` == 0
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Trap-Vector Base Address (``mtvec``) - ``CLIC`` == 0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x305
 
@@ -687,10 +687,10 @@ Upon an NMI in vectored CLINT mode the core jumps to **mtvec[31:7]**, 5'hF, 2'b0
 .. note::
    Memory writes to the ``mtvec`` based vector table require an instruction barrier (``fence.i``) to guarantee that they are visible to the instruction fetch (see :ref:`fencei` and [RISC-V-UNPRIV]_).
 
-.. _csr-mtvec-smclic:
+.. _csr-mtvec-clic:
 
-Machine Trap-Vector Base Address (``mtvec``) - ``SMCLIC`` == 1
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Trap-Vector Base Address (``mtvec``) - ``CLIC`` == 1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x305
 
@@ -730,7 +730,7 @@ CSR Address: 0x307
 
 Reset Value: 0x0000_0000
 
-Include Condition: ``SMCLIC`` = 1
+Include Condition: ``CLIC`` = 1
 
 Detailed:
 
@@ -742,12 +742,12 @@ Detailed:
   |   Bit #     |   R/W      |           Description                                                 |
   +=============+============+=======================================================================+
   | 31:N        | RW         | **BASE[31:N]**: Trap-handler vector table base address.               |
-  |             |            | N = maximum(6, 2+SMCLIC_ID_WIDTH).                                    |
+  |             |            | N = maximum(6, 2+CLIC_ID_WIDTH).                                      |
   |             |            | See note below for alignment restrictions.                            |
   +-------------+------------+-----------------------------------------------------------------------+
   | N-1:6       | WARL (0x0) | **BASE[N-1:6]**: Trap-handler vector table base address.              |
   |             |            | This field is only defined if N > 6.                                  |
-  |             |            | N = maximum(6, 2+SMCLIC_ID_WIDTH).                                    |
+  |             |            | N = maximum(6, 2+CLIC_ID_WIDTH).                                      |
   |             |            | ``mtvt[N-1:6]`` is hardwired to 0x0.                                  |
   |             |            | See note below for  alignment restrictions.                           |
   +-------------+------------+-----------------------------------------------------------------------+
@@ -756,7 +756,7 @@ Detailed:
 
 .. note::
    The ``mtvt`` CSR holds the base address of the trap vector table, which has its alignment restricted to both at least 64-bytes and to
-   ``2^(2+SMCLIC_ID_WIDTH)`` bytes or greater power-of-two boundary. For example if ``SMCLIC_ID_WIDTH`` = 8, then 256 CLIC interrupts are supported and the trap vector table
+   ``2^(2+CLIC_ID_WIDTH)`` bytes or greater power-of-two boundary. For example if ``CLIC_ID_WIDTH`` = 8, then 256 CLIC interrupts are supported and the trap vector table
    is aligned to 1024 bytes, and therefore **BASE[9:6]** will be WARL (0x0).
 
 .. note::
@@ -1116,8 +1116,8 @@ in MEPC, and the core jumps to the exception address. When a mret
 instruction is executed, the value from MEPC replaces the current
 program counter.
 
-Machine Cause (``mcause``) - ``SMCLIC`` == 0
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Cause (``mcause``) - ``CLIC`` == 0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x342
 
@@ -1142,8 +1142,8 @@ Reset Value: 0x0000_0000
    Software accesses to `mcause[10:0]` must be sensitive to the WLRL field specification of this CSR.  For example,
    when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
 
-Machine Cause (``mcause``) - ``SMCLIC`` == 1
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Cause (``mcause``) - ``CLIC`` == 1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x342
 
@@ -1200,8 +1200,8 @@ Detailed:
   | 31:0        | WARL (0x0) | Hardwired to 0.                                                        |
   +-------------+------------+------------------------------------------------------------------------+
 
-Machine Interrupt Pending Register (``mip``) - ``SMCLIC`` == 0
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Interrupt Pending Register (``mip``) - ``CLIC`` == 0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x344
 
@@ -1245,8 +1245,8 @@ Detailed:
   |  0          | WARL (0x0)| Reserved. Hardwired to 0.                                                                |
   +-------------+-----------+------------------------------------------------------------------------------------------+
 
-Machine Interrupt Pending Register (``mip``) - ``SMCLIC`` == 1
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Machine Interrupt Pending Register (``mip``) - ``CLIC`` == 1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x344
 
@@ -1276,7 +1276,7 @@ CSR Address: 0x345
 
 Reset Value: 0x0000_0000
 
-Include Condition: ``SMCLIC`` = 1
+Include Condition: ``CLIC`` = 1
 
 Detailed:
 
@@ -1307,7 +1307,7 @@ CSR Address: 0x347
 
 Reset Value: 0x0000_0000
 
-Include Condition: ``SMCLIC`` = 1
+Include Condition: ``CLIC`` = 1
 
 Detailed:
 
@@ -1326,7 +1326,7 @@ Detailed:
 This register holds the machine mode interrupt level threshold.
 
 .. note::
-  The ``SMCLIC_INTTHRESHBITS`` parameter specifies the number of bits actually implemented in the ``mintthresh.th`` field.
+  The ``CLIC_INTTHRESHBITS`` parameter specifies the number of bits actually implemented in the ``mintthresh.th`` field.
   The implemented bits are kept left justified in the most-significant bits of the 8-bit field, with the lower unimplemented
   bits treated as hardwired to 1.
 
@@ -1339,7 +1339,7 @@ CSR Address: 0x348
 
 Reset Value: 0x0000_0000
 
-Include Condition: ``SMCLIC`` = 1
+Include Condition: ``CLIC`` = 1
 
 Detailed:
 
@@ -1369,7 +1369,7 @@ CSR Address: 0x349
 
 Reset Value: 0x0000_0000
 
-Include Condition: ``SMCLIC`` = 1
+Include Condition: ``CLIC`` = 1
 
 Detailed:
 
@@ -2190,11 +2190,11 @@ Detailed:
 Machine Interrupt Status (``mintstatus``)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-CSR Address: 0xF46
+CSR Address: 0xFB1
 
 Reset Value: 0x0000_0000
 
-Include Condition: ``SMCLIC`` = 1
+Include Condition: ``CLIC`` = 1
 
 Detailed:
 

docs/user_manual/source/exceptions_interrupts.rst

@@ -4,8 +4,8 @@ Exceptions and Interrupts
 =========================
 
 |corev| supports one of two interrupt architectures.
-If the ``SMCLIC`` parameter is set to 0, then the CLINT mode interrupt architecture is supported (see :ref:`clint_interrupt_architecture`).
-If the ``SMCLIC`` parameter is set to 1, then the CLIC mode interrupt architecture is supported (see :ref:`clic_interrupt_architecture`).
+If the ``CLIC`` parameter is set to 0, then the CLINT mode interrupt architecture is supported (see :ref:`clint_interrupt_architecture`).
+If the ``CLIC`` parameter is set to 1, then the CLIC mode interrupt architecture is supported (see :ref:`clic_interrupt_architecture`).
 
 Exceptions
 ----------
@@ -83,12 +83,12 @@ Non Maskable Interrupts (NMIs) update ``mepc``, ``mcause`` and ``mstatus`` simil
 
 NMIs have higher priority than other interrupts for both the CLINT mode interrupt architecture and the CLIC mode interrupt architecture.
 
-If ``SMCLIC`` == 0, then the NMI vector location is as follows:
+If ``CLIC`` == 0, then the NMI vector location is as follows:
 
 * Upon an NMI in non-vectored CLINT mode the core jumps to **mtvec[31:7]**, 5'h0, 2'b00} (i.e. index 0).
 * Upon an NMI in vectored CLINT mode the core jumps to **mtvec[31:7]**, 5'hF, 2'b00} (i.e. index 15).
 
-If ``SMCLIC`` == 1, then the NMI vector location is as follows:
+If ``CLIC`` == 1, then the NMI vector location is as follows:
 
 * Upon an NMI in CLIC mode the core jumps to **mtvec[31:7]**, 5'h0, 2'b00} (i.e. index 0).
 
@@ -114,7 +114,7 @@ While an NMI is pending, ``DCSR.nmip`` will be 1. Note that this CSR is only acc
 CLINT Mode Interrupt Architecture
 ---------------------------------
 
-If ``SMCLIC`` == 0, then |corev| supports the CLINT mode interrupt architecture as defined in [RISC-V-PRIV]_. In this configuration only the
+If ``CLIC`` == 0, then |corev| supports the CLINT mode interrupt architecture as defined in [RISC-V-PRIV]_. In this configuration only the
 CLINT mode interrupt handling modes (non-vectored CLINT mode and vectored CLINT mode) can be used. The ``irq_i[31:16]`` interrupts are a custom extension
 that can be used with the CLINT mode interrupt architecture.
 
@@ -249,10 +249,10 @@ To allow higher priority interrupts only, the handler must configure ``mie`` acc
 CLIC Mode Interrupt Architecture
 --------------------------------
 
-If ``SMCLIC`` == 1, then |corev| supports the Core-Local Interrupt Controller (CLIC) Privileged Architecture Extension defined in [RISC-V-SMCLIC]_. In this
-configuration only the CLIC interrupt handling mode can be used (i.e. ``mtvec[1:0]`` = 0x3).
+If ``CLIC`` == 1, then |corev| supports the  Smclic, Smclicshv and Smclicconfig extensions defined in [RISC-V-CLIC]_. The Ssclic and Suclic extensions are not supported.
+In this configuration (i.e. ``CLIC`` == 1) only the CLIC interrupt handling mode can be used (i.e. ``mtvec[1:0]`` = 0x3).
 
-The CLIC implementation is split into a part internal to the core (containing CSRs and related logic) and a part external to the core (containing memory mapped registers and arbitration logic). |corev| only
+The CLIC implementation is however split into a part internal to the core (containing CSRs and related logic) and a part external to the core (containing memory mapped registers and arbitration logic). |corev| **only**
 provides the core internal part of CLIC. The external part can be added on the interface described in :ref:`clic-interrupt-interface`. CLIC provides low-latency, vectored, pre-emptive interrupts.
 
 .. _clic-interrupt-interface:
@@ -272,7 +272,7 @@ Interrupt Interface
   +========================================+===========+==================================================+
   | ``clic_irq_i``                         | input     | Is there any pending-and-enabled interrupt?      |
   +----------------------------------------+-----------+--------------------------------------------------+
-  | ``clic_irq_id_i[SMCLIC_ID_WIDTH-1:0]`` | input     | Index of the most urgent pending-and-enabled     |
+  | ``clic_irq_id_i[CLIC_ID_WIDTH-1:0]``   | input     | Index of the most urgent pending-and-enabled     |
   |                                        |           | interrupt.                                       |
   +----------------------------------------+-----------+--------------------------------------------------+
   | ``clic_irq_level_i[7:0]``              | input     | Interrupt level of the most urgent               |
@@ -287,7 +287,7 @@ Interrupt Interface
   +----------------------------------------+-----------+--------------------------------------------------+
 
 The term *pending-and-enabled* interrupt in above table refers to *pending-and-locally-enabled*, i.e. based on the ``CLICINTIP`` and
-``CLICINTIE`` memory mapped registers from [RISC-V-SMCLIC]_.
+``CLICINTIE`` memory mapped registers from [RISC-V-CLIC]_.
 
 .. note::
 
@@ -307,15 +307,15 @@ The term *pending-and-enabled* interrupt in above table refers to *pending-and-l
 
 Interrupts
 ~~~~~~~~~~
-Although the [RISC-V-SMCLIC]_ specification supports up to 4096 interrupts, |corev| itself supports at most 1024 interrupts. The
-maximum number of supported CLIC interrupts is equal to ``2^SMCLIC_ID_WIDTH``, which can range from 2 to 1024. The ``SMCLIC_ID_WIDTH`` parameter
+Although the [RISC-V-CLIC]_ specification supports up to 4096 interrupts, |corev| itself supports at most 1024 interrupts. The
+maximum number of supported CLIC interrupts is equal to ``2^CLIC_ID_WIDTH``, which can range from 2 to 1024. The ``CLIC_ID_WIDTH`` parameter
 also impacts the alignment requirement for the trap vector table, see :ref:`csr-mtvt`.
 
 Interrupt prioritization is mostly performed in the part of CLIC that is external to the core, with the exception that |corev| prioritizes all NMIs above interrupts received via ``clic_irq_i``.
 
 Nested Interrupt Handling
 ~~~~~~~~~~~~~~~~~~~~~~~~~
-|corev| offers hardware support for nested interrupt handling when ``SMCLIC`` == 1. 
+|corev| offers hardware support for nested interrupt handling when ``CLIC`` == 1. 
 
 CLIC extends interrupt preemption to support up to 256 interrupt levels for each privilege mode,
-where higher-numbered interrupt levels can preempt lower-numbered interrupt levels. See [RISC-V-SMCLIC]_ for details.
+where higher-numbered interrupt levels can preempt lower-numbered interrupt levels. See [RISC-V-CLIC]_ for details.