Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Changes needed for SDP MSPI #2260

Merged
merged 3 commits into from
Jan 8, 2025
+90 −1
Merged

Changes needed for SDP MSPI #2260

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
b82f98d
[nrf fromlist] tests: drivers: mspi: make MSPI API test more generic
jaz1-nordic Nov 27, 2024
91eaae3
[nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration
jaz1-nordic Nov 25, 2024
d6174e0
[nrf noup] tests: drivers: mspi: api: Add nRF54L15 overlay file
jaz1-nordic Nov 25, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
29 changes: 29 additions & 0 deletions drivers/pinctrl/pinctrl_nrf.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,13 @@
#endif
#endif

#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE)
#define NRF_PSEL_SDP_MSPI(psel) \
nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
#endif

Check notice on line 110 in drivers/pinctrl/pinctrl_nrf.c

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

You may want to run clang-format on this change 

drivers/pinctrl/pinctrl_nrf.c:110 
-#define NRF_PSEL_SDP_MSPI(psel)                                                                    \
-	nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
+#define NRF_PSEL_SDP_MSPI(psel) nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
Expand Down Expand Up @@ -393,6 +400,28 @@
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_exmif) */
#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller)
case NRF_FUN_SDP_MSPI_CS0:
case NRF_FUN_SDP_MSPI_CS1:
case NRF_FUN_SDP_MSPI_CS2:
case NRF_FUN_SDP_MSPI_CS3:
case NRF_FUN_SDP_MSPI_CS4:
case NRF_FUN_SDP_MSPI_SCK:
case NRF_FUN_SDP_MSPI_DQ0:
case NRF_FUN_SDP_MSPI_DQ1:
case NRF_FUN_SDP_MSPI_DQ2:
case NRF_FUN_SDP_MSPI_DQ3:
case NRF_FUN_SDP_MSPI_DQ4:
case NRF_FUN_SDP_MSPI_DQ5:
case NRF_FUN_SDP_MSPI_DQ6:
case NRF_FUN_SDP_MSPI_DQ7:
NRF_PSEL_SDP_MSPI(psel);
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
Comment on lines +420 to +421
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Are there any expectations in VIO regarding pre-configuration by GPIO peripheral?
I'm wondering about the nrf_gpio_pin_write and nrf_gpio_cfg below.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do you mean to setup for example polarity of the clk signal?

break;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */
#endif /* CONFIG_SOC_NRF54L15_CPUAPP */
default:
return -ENOTSUP;
}
Expand Down
28 changes: 28 additions & 0 deletions include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -168,7 +168,35 @@
#define NRF_FUN_GRTC_CLKOUT_FAST 55U
/** GRTC slow clock output */
#define NRF_FUN_GRTC_CLKOUT_32K 56U
/** SDP_MSPI CK */
#define NRF_FUN_SDP_MSPI_SCK 57U
/** SDP_MSPI DQ0 */
#define NRF_FUN_SDP_MSPI_DQ0 58U
/** SDP_MSPI DQ1 */
#define NRF_FUN_SDP_MSPI_DQ1 59U
/** SDP_MSPI DQ2 */
#define NRF_FUN_SDP_MSPI_DQ2 60U
/** SDP_MSPI DQ3 */
#define NRF_FUN_SDP_MSPI_DQ3 61U
/** SDP_MSPI DQ4 */
#define NRF_FUN_SDP_MSPI_DQ4 62U
/** SDP_MSPI DQ5 */
#define NRF_FUN_SDP_MSPI_DQ5 63U
/** SDP_MSPI DQ6 */
#define NRF_FUN_SDP_MSPI_DQ6 64U
/** SDP_MSPI DQ7 */
#define NRF_FUN_SDP_MSPI_DQ7 65U
/** SDP_MSPI CS0 */
#define NRF_FUN_SDP_MSPI_CS0 66U
/** SDP_MSPI CS1 */
#define NRF_FUN_SDP_MSPI_CS1 67U
/** SDP_MSPI CS2 */
#define NRF_FUN_SDP_MSPI_CS2 68U
/** SDP_MSPI CS3 */
#define NRF_FUN_SDP_MSPI_CS3 69U
/** SDP_MSPI CS4 */
#define NRF_FUN_SDP_MSPI_CS4 70U

Check notice on line 199 in include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

You may want to run clang-format on this change 

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h:199 
-#define NRF_FUN_SDP_MSPI_SCK 57U
+#define NRF_FUN_SDP_MSPI_SCK     57U
 /** SDP_MSPI DQ0 */
-#define NRF_FUN_SDP_MSPI_DQ0 58U
+#define NRF_FUN_SDP_MSPI_DQ0     58U
 /** SDP_MSPI DQ1 */
-#define NRF_FUN_SDP_MSPI_DQ1 59U
+#define NRF_FUN_SDP_MSPI_DQ1     59U
 /** SDP_MSPI DQ2 */
-#define NRF_FUN_SDP_MSPI_DQ2 60U
+#define NRF_FUN_SDP_MSPI_DQ2     60U
 /** SDP_MSPI DQ3 */
-#define NRF_FUN_SDP_MSPI_DQ3 61U
+#define NRF_FUN_SDP_MSPI_DQ3     61U
 /** SDP_MSPI DQ4 */
-#define NRF_FUN_SDP_MSPI_DQ4 62U
+#define NRF_FUN_SDP_MSPI_DQ4     62U
 /** SDP_MSPI DQ5 */
-#define NRF_FUN_SDP_MSPI_DQ5 63U
+#define NRF_FUN_SDP_MSPI_DQ5     63U
 /** SDP_MSPI DQ6 */
-#define NRF_FUN_SDP_MSPI_DQ6 64U
+#define NRF_FUN_SDP_MSPI_DQ6     64U
 /** SDP_MSPI DQ7 */
-#define NRF_FUN_SDP_MSPI_DQ7 65U
+#define NRF_FUN_SDP_MSPI_DQ7     65U
 /** SDP_MSPI CS0 */
-#define NRF_FUN_SDP_MSPI_CS0 66U
+#define NRF_FUN_SDP_MSPI_CS0     66U
 /** SDP_MSPI CS1 */
-#define NRF_FUN_SDP_MSPI_CS1 67U
+#define NRF_FUN_SDP_MSPI_CS1     67U
 /** SDP_MSPI CS2 */
-#define NRF_FUN_SDP_MSPI_CS2 68U
+#define NRF_FUN_SDP_MSPI_CS2     68U
 /** SDP_MSPI CS3 */
-#define NRF_FUN_SDP_MSPI_CS3 69U
+#define NRF_FUN_SDP_MSPI_CS3     69U
 /** SDP_MSPI CS4 */
-#define NRF_FUN_SDP_MSPI_CS4 70U
+#define NRF_FUN_SDP_MSPI_CS4     70U
/** @} */

/**
Expand Down
24 changes: 24 additions & 0 deletions tests/drivers/mspi/api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/

/ {
aliases {
mspi0 = &sdp_mspi;
};
};

&cpuflpr_vpr {
status = "okay";

sdp_mspi: sdp_mspi {
mspi_device: mspi_device@0 {
status = "okay";
compatible = "zephyr,mspi-emul-device";
reg = <0x0>;
mspi-max-frequency = <48000000>;
};
};
};
10 changes: 9 additions & 1 deletion tests/drivers/mspi/api/src/main.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -51,13 +51,17 @@ static struct mspi_dev_cfg device_cfg[] = {
DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_DEVICE_CONFIG_DT, (,))
};

#if CONFIG_MSPI_XIP
jaz1-nordic marked this conversation as resolved.
Show resolved Hide resolved
static struct mspi_xip_cfg xip_cfg[] = {
DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_XIP_CONFIG_DT, (,))
};
#endif

#if CONFIG_MSPI_SCRAMBLE
static struct mspi_scramble_cfg scramble_cfg[] = {
DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_SCRAMBLE_CONFIG_DT, (,))
};
#endif

ZTEST(mspi_api, test_mspi_api)
{
Expand Down Expand Up @@ -104,7 +108,11 @@ ZTEST(mspi_api, test_mspi_api)

ret = mspi_register_callback(mspi_bus, &dev_id[dev_idx],
MSPI_BUS_XFER_COMPLETE, NULL, NULL);
zassert_equal(ret, 0, "mspi_register_callback failed.");
if (ret == -ENOTSUP) {
printf("mspi_register_callback not supported.\n");
} else {
zassert_equal(ret, 0, "mspi_register_callback failed.");
}

ret = mspi_get_channel_status(mspi_bus, 0);
zassert_equal(ret, 0, "mspi_get_channel_status failed.");
Expand Down
Loading