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Enable multiple synchronized bitfiles in the RT engine #28

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merged 12 commits into from
Jan 29, 2019
+82,928 −4
Merged

Enable multiple synchronized bitfiles in the RT engine #28

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f962505
Adding configuration code for multiple bitfiles
buckd Jan 16, 2019
fefe820
Actually use multi-fpga initialization code
buckd Jan 16, 2019
7595974
Add multi-fpga support for engine execution
buckd Jan 18, 2019
add47bf
Merge branch 'master' into dev/multi-bitfile-engine
buckd Jan 24, 2019
0154bd0
Fix register names when compiling APU data
buckd Jan 24, 2019
e59860e
Bump custom device version in XML
buckd Jan 24, 2019
63882d0
Revert version bump. This already happened for this feature.
buckd Jan 25, 2019
c2bfd51
Merge branch 'master' into dev/multi-bitfile-engine
buckd Jan 25, 2019
3f64a9d
Don't show compile VI during deployment (remove debugging)
buckd Jan 25, 2019
af92e50
Remove unused FPGA run VI
buckd Jan 25, 2019
9aada91
Only read the multi-fpga feature toggle from the ini key in On Load
rtzoeller Jan 28, 2019
9ddb67c
Add synchronization test for multiple FPGAs
buckd Jan 28, 2019
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4 changes: 4 additions & 0 deletions Source/Engine Simulation Toolkit Custom Device.lvproj
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Expand Up @@ -1028,6 +1028,7 @@
<Item Name="Dependencies" Type="Dependencies">
<Item Name="vi.lib" Type="Folder">
<Item Name="Check Special Tags.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Check Special Tags.vi"/>
<Item Name="Clear Errors.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Clear Errors.vi"/>
<Item Name="Custom Device API.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device API/Custom Device API.lvlib"/>
<Item Name="Custom Device Utility Library.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device Tools/Custom Device Utility Library/Custom Device Utility Library.lvlib"/>
<Item Name="Error Cluster From Error Code.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Error Cluster From Error Code.vi"/>
Expand Down Expand Up @@ -1238,6 +1239,7 @@ DirectoryIndex index.htm
<Item Name="Dependencies" Type="Dependencies">
<Item Name="vi.lib" Type="Folder">
<Item Name="Check Special Tags.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Check Special Tags.vi"/>
<Item Name="Clear Errors.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Clear Errors.vi"/>
<Item Name="Custom Device API.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device API/Custom Device API.lvlib"/>
<Item Name="Custom Device Utility Library.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device Tools/Custom Device Utility Library/Custom Device Utility Library.lvlib"/>
<Item Name="Error Cluster From Error Code.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Error Cluster From Error Code.vi"/>
Expand Down Expand Up @@ -1450,6 +1452,7 @@ AddOutputFilter chunkFilter
<Item Name="Dependencies" Type="Dependencies">
<Item Name="vi.lib" Type="Folder">
<Item Name="Check Special Tags.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Check Special Tags.vi"/>
<Item Name="Clear Errors.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Clear Errors.vi"/>
<Item Name="Custom Device API.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device API/Custom Device API.lvlib"/>
<Item Name="Custom Device Utility Library.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device Tools/Custom Device Utility Library/Custom Device Utility Library.lvlib"/>
<Item Name="Error Cluster From Error Code.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Error Cluster From Error Code.vi"/>
Expand Down Expand Up @@ -1643,6 +1646,7 @@ AddOutputFilter chunkFilter
<Item Name="Dependencies" Type="Dependencies">
<Item Name="vi.lib" Type="Folder">
<Item Name="Check Special Tags.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Check Special Tags.vi"/>
<Item Name="Clear Errors.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Clear Errors.vi"/>
<Item Name="Custom Device API.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device API/Custom Device API.lvlib"/>
<Item Name="Custom Device Utility Library.lvlib" Type="Library" URL="/&lt;vilib&gt;/NI VeriStand/Custom Device Tools/Custom Device Utility Library/Custom Device Utility Library.lvlib"/>
<Item Name="Error Cluster From Error Code.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Error Cluster From Error Code.vi"/>
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39 changes: 38 additions & 1 deletion Source/Engine/Engine Simulation Toolkit Engine.lvlib
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Expand Up @@ -19,7 +19,9 @@
<Item Name="Analog Replay 1.0 FPGA Inputs Write Node.vi" Type="VI" URL="../Analog Replay 1.0 FPGA Inputs Write Node.vi"/>
<Item Name="Analog Replay 1.0 In Place Input Write Structure.vi" Type="VI" URL="../Analog Replay 1.0 In Place Input Write Structure.vi"/>
<Item Name="Analog Replay 1.0 Init.vi" Type="VI" URL="../Analog Replay 1.0 Init.vi"/>
<Item Name="Analog Replay 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Analog Replay 1.0 Init - Multi FPGA.vi"/>
<Item Name="Analog Replay 1.0 Run.vi" Type="VI" URL="../Analog Replay 1.0 Run.vi"/>
<Item Name="Analog Replay 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Analog Replay 1.0 Run - Multi FPGA.vi"/>
<Item Name="Analog Replay 1.0 Voltage Scaling.vi" Type="VI" URL="../Analog Replay 1.0 Voltage Scaling.vi"/>
</Item>
</Item>
Expand All @@ -36,8 +38,10 @@
<Item Name="APU 1.0 In Place Input Write Structure.vi" Type="VI" URL="../APU 1.0 In Place Input Write Structure.vi"/>
<Item Name="APU 1.0 In Place Output Read Structure.vi" Type="VI" URL="../APU 1.0 In Place Output Read Structure.vi"/>
<Item Name="APU 1.0 Init.vi" Type="VI" URL="../APU 1.0 Init.vi"/>
<Item Name="APU 1.0 Init - Multi FPGA.vi" Type="VI" URL="../APU 1.0 Init - Multi FPGA.vi"/>
<Item Name="APU 1.0 Read Outputs.vi" Type="VI" URL="../APU 1.0 Read Outputs.vi"/>
<Item Name="APU 1.0 Run.vi" Type="VI" URL="../APU 1.0 Run.vi"/>
<Item Name="APU 1.0 Run - Multi FPGA.vi" Type="VI" URL="../APU 1.0 Run - Multi FPGA.vi"/>
<Item Name="APU 1.0 Write Inputs.vi" Type="VI" URL="../APU 1.0 Write Inputs.vi"/>
</Item>
<Item Name="1.1" Type="Folder">
Expand All @@ -47,7 +51,9 @@
<Item Name="APU 1.1 In Place Input Write Structure.vi" Type="VI" URL="../APU 1.1 In Place Input Write Structure.vi"/>
<Item Name="APU 1.1 In Place Output Read Structure.vi" Type="VI" URL="../APU 1.1 In Place Output Read Structure.vi"/>
<Item Name="APU 1.1 Init.vi" Type="VI" URL="../APU 1.1 Init.vi"/>
<Item Name="APU 1.1 Init - Multi FPGA.vi" Type="VI" URL="../APU 1.1 Init - Multi FPGA.vi"/>
<Item Name="APU 1.1 Run.vi" Type="VI" URL="../APU 1.1 Run.vi"/>
<Item Name="APU 1.1 Run - Multi FPGA.vi" Type="VI" URL="../APU 1.1 Run - Multi FPGA.vi"/>
</Item>
<Item Name="1.3" Type="Folder">
<Item Name="Types" Type="Folder">
Expand All @@ -57,19 +63,32 @@
<Item Name="APU 1.3 In Place Input Write Structure.vi" Type="VI" URL="../APU 1.3 In Place Input Write Structure.vi"/>
<Item Name="APU 1.3 In Place Output Read Structure.vi" Type="VI" URL="../APU 1.3 In Place Output Read Structure.vi"/>
<Item Name="APU 1.3 Init.vi" Type="VI" URL="../APU 1.3 Init.vi"/>
<Item Name="APU 1.3 Init - Multi FPGA.vi" Type="VI" URL="../APU 1.3 Init - Multi FPGA.vi"/>
<Item Name="APU 1.3 Run.vi" Type="VI" URL="../APU 1.3 Run.vi"/>
<Item Name="APU 1.3 Run - Multi FPGA.vi" Type="VI" URL="../APU 1.3 Run - Multi FPGA.vi"/>
</Item>
<Item Name="1.4" Type="Folder">
<Item Name="APU 1.4 In Place Input Write Structure.vi" Type="VI" URL="../APU 1.4 In Place Input Write Structure.vi"/>
<Item Name="APU 1.4 In Place Output Read Structure.vi" Type="VI" URL="../APU 1.4 In Place Output Read Structure.vi"/>
<Item Name="APU 1.4 Init - Multi FPGA.vi" Type="VI" URL="../APU 1.4 Init - Multi FPGA.vi"/>
<Item Name="APU 1.4 Init Master.vi" Type="VI" URL="../APU 1.4 Init Master.vi"/>
<Item Name="APU 1.4 Read Outputs.vi" Type="VI" URL="../APU 1.4 Read Outputs.vi"/>
<Item Name="APU 1.4 Run - Multi FPGA.vi" Type="VI" URL="../APU 1.4 Run - Multi FPGA.vi"/>
</Item>
<Item Name="APU FXP Speed to DBL Speed.vi" Type="VI" URL="../APU FXP Speed to DBL Speed.vi"/>
<Item Name="Synchronize APUs.vi" Type="VI" URL="../Synchronize APUs.vi"/>
</Item>
<Item Name="Bitfile" Type="Folder">
<Item Name="Close all FPGA refs.vi" Type="VI" URL="../Close all FPGA refs.vi"/>
<Item Name="FPGA run method.vi" Type="VI" URL="../FPGA run method.vi"/>
<Item Name="Init Bitfile.vi" Type="VI" URL="../Init Bitfile.vi"/>
<Item Name="Init Multiple Bitfiles.vi" Type="VI" URL="../Init Multiple Bitfiles.vi"/>
<Item Name="Run Bitfile.vi" Type="VI" URL="../Run Bitfile.vi"/>
<Item Name="Run Multiple Bitfiles.vi" Type="VI" URL="../Run Multiple Bitfiles.vi"/>
</Item>
<Item Name="Communication" Type="Folder">
<Item Name="Read VS FIFO.vi" Type="VI" URL="../Read VS FIFO.vi"/>
<Item Name="Write VS FIFO.vi" Type="VI" URL="../Write VS FIFO.vi"/>
<Item Name="Write VS FIFO - Multi FPGA.vi" Type="VI" URL="../Write VS FIFO - Multi FPGA.vi"/>
</Item>
<Item Name="Digital Pattern Gen" Type="Folder">
<Item Name="1.0" Type="Folder">
Expand All @@ -81,7 +100,9 @@
<Item Name="Digital Pattern Gen 1.0 FPGA Inputs Write Node.vi" Type="VI" URL="../Digital Pattern Gen 1.0 FPGA Inputs Write Node.vi"/>
<Item Name="Digital Pattern Gen 1.0 In Place Input Write Structure.vi" Type="VI" URL="../Digital Pattern Gen 1.0 In Place Input Write Structure.vi"/>
<Item Name="Digital Pattern Gen 1.0 Init.vi" Type="VI" URL="../Digital Pattern Gen 1.0 Init.vi"/>
<Item Name="Digital Pattern Gen 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Digital Pattern Gen 1.0 Init - Multi FPGA.vi"/>
<Item Name="Digital Pattern Gen 1.0 Run.vi" Type="VI" URL="../Digital Pattern Gen 1.0 Run.vi"/>
<Item Name="Digital Pattern Gen 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Digital Pattern Gen 1.0 Run - Multi FPGA.vi"/>
<Item Name="Digital Pattern Gen 1.0 Write Inputs.vi" Type="VI" URL="../Digital Pattern Gen 1.0 Write Inputs.vi"/>
</Item>
<Item Name="1.3" Type="Folder">
Expand All @@ -93,7 +114,9 @@
<Item Name="Digital Pattern Gen 1.3 In Place Input Write Structure.vi" Type="VI" URL="../Digital Pattern Gen 1.3 In Place Input Write Structure.vi"/>
<Item Name="Digital Pattern Gen 1.3 In Place Settings Write Structure.vi" Type="VI" URL="../Digital Pattern Gen 1.3 In Place Settings Write Structure.vi"/>
<Item Name="Digital Pattern Gen 1.3 Init.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Init.vi"/>
<Item Name="Digital Pattern Gen 1.3 Init - Multi FPGA.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Init - Multi FPGA.vi"/>
<Item Name="Digital Pattern Gen 1.3 Run.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Run.vi"/>
<Item Name="Digital Pattern Gen 1.3 Run - Multi FPGA.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Run - Multi FPGA.vi"/>
<Item Name="Digital Pattern Gen 1.3 Tooth to Edges.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Tooth to Edges.vi"/>
<Item Name="Digital Pattern Gen 1.3 Validate Fault Positions.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Validate Fault Positions.vi"/>
<Item Name="Digital Pattern Gen 1.3 Write Inputs.vi" Type="VI" URL="../Digital Pattern Gen 1.3 Write Inputs.vi"/>
Expand All @@ -109,7 +132,9 @@
<Item Name="Directional Speed 1.0 FPGA Inputs Write Node.vi" Type="VI" URL="../Directional Speed 1.0 FPGA Inputs Write Node.vi"/>
<Item Name="Directional Speed 1.0 In Place Input Write Structure.vi" Type="VI" URL="../Directional Speed 1.0 In Place Input Write Structure.vi"/>
<Item Name="Directional Speed 1.0 Init.vi" Type="VI" URL="../Directional Speed 1.0 Init.vi"/>
<Item Name="Directional Speed 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Directional Speed 1.0 Init - Multi FPGA.vi"/>
<Item Name="Directional Speed 1.0 Run.vi" Type="VI" URL="../Directional Speed 1.0 Run.vi"/>
<Item Name="Directional Speed 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Directional Speed 1.0 Run - Multi FPGA.vi"/>
<Item Name="Directional Speed 1.0 Write Inputs.vi" Type="VI" URL="../Directional Speed 1.0 Write Inputs.vi"/>
</Item>
</Item>
Expand All @@ -121,7 +146,9 @@
</Item>
<Item Name="Event Timing Capture 1.0 In Place Output Read Structure.vi" Type="VI" URL="../Event Timing Capture 1.0 In Place Output Read Structure.vi"/>
<Item Name="Event Timing Capture 1.0 Init.vi" Type="VI" URL="../Event Timing Capture 1.0 Init.vi"/>
<Item Name="Event Timing Capture 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Event Timing Capture 1.0 Init - Multi FPGA.vi"/>
<Item Name="Event Timing Capture 1.0 Run.vi" Type="VI" URL="../Event Timing Capture 1.0 Run.vi"/>
<Item Name="Event Timing Capture 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Event Timing Capture 1.0 Run - Multi FPGA.vi"/>
</Item>
</Item>
<Item Name="Measure" Type="Folder">
Expand All @@ -132,15 +159,19 @@
</Item>
<Item Name="Event Timing Measure 1.0 In Place Output Read Structure.vi" Type="VI" URL="../Event Timing Measure 1.0 In Place Output Read Structure.vi"/>
<Item Name="Event Timing Measure 1.0 Init.vi" Type="VI" URL="../Event Timing Measure 1.0 Init.vi"/>
<Item Name="Event Timing Measure 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Event Timing Measure 1.0 Init - Multi FPGA.vi"/>
<Item Name="Event Timing Measure 1.0 Run.vi" Type="VI" URL="../Event Timing Measure 1.0 Run.vi"/>
<Item Name="Event Timing Measure 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Event Timing Measure 1.0 Run - Multi FPGA.vi"/>
</Item>
<Item Name="1.1" Type="Folder">
<Item Name="Types" Type="Folder">
<Item Name="Event Timing Measure 1.1 Settings Ref.ctl" Type="VI" URL="../Event Timing Measure 1.1 Settings Ref.ctl"/>
</Item>
<Item Name="Event Timing Measure 1.1 In Place Output Read Structure.vi" Type="VI" URL="../Event Timing Measure 1.1 In Place Output Read Structure.vi"/>
<Item Name="Event Timing Measure 1.1 Init.vi" Type="VI" URL="../Event Timing Measure 1.1 Init.vi"/>
<Item Name="Event Timing Measure 1.1 Init - Multi FPGA.vi" Type="VI" URL="../Event Timing Measure 1.1 Init - Multi FPGA.vi"/>
<Item Name="Event Timing Measure 1.1 Run.vi" Type="VI" URL="../Event Timing Measure 1.1 Run.vi"/>
<Item Name="Event Timing Measure 1.1 Run - Multi FPGA.vi" Type="VI" URL="../Event Timing Measure 1.1 Run - Multi FPGA.vi"/>
</Item>
</Item>
</Item>
Expand All @@ -154,7 +185,9 @@
<Item Name="Knock Cylinder 1.0 FPGA Inputs Write Node.vi" Type="VI" URL="../Knock Cylinder 1.0 FPGA Inputs Write Node.vi"/>
<Item Name="Knock Cylinder 1.0 In Place Input Write Structure.vi" Type="VI" URL="../Knock Cylinder 1.0 In Place Input Write Structure.vi"/>
<Item Name="Knock Cylinder 1.0 Init.vi" Type="VI" URL="../Knock Cylinder 1.0 Init.vi"/>
<Item Name="Knock Cylinder 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Knock Cylinder 1.0 Init - Multi FPGA.vi"/>
<Item Name="Knock Cylinder 1.0 Run.vi" Type="VI" URL="../Knock Cylinder 1.0 Run.vi"/>
<Item Name="Knock Cylinder 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Knock Cylinder 1.0 Run - Multi FPGA.vi"/>
<Item Name="Knock Cylinder 1.0 Write Inputs.vi" Type="VI" URL="../Knock Cylinder 1.0 Write Inputs.vi"/>
</Item>
</Item>
Expand All @@ -167,7 +200,9 @@
<Item Name="Knock Sensor 1.0 FPGA Inputs Write Node.vi" Type="VI" URL="../Knock Sensor 1.0 FPGA Inputs Write Node.vi"/>
<Item Name="Knock Sensor 1.0 In Place Input Write Structure.vi" Type="VI" URL="../Knock Sensor 1.0 In Place Input Write Structure.vi"/>
<Item Name="Knock Sensor 1.0 Init.vi" Type="VI" URL="../Knock Sensor 1.0 Init.vi"/>
<Item Name="Knock Sensor 1.0 Init - Multi FPGA.vi" Type="VI" URL="../Knock Sensor 1.0 Init - Multi FPGA.vi"/>
<Item Name="Knock Sensor 1.0 Run.vi" Type="VI" URL="../Knock Sensor 1.0 Run.vi"/>
<Item Name="Knock Sensor 1.0 Run - Multi FPGA.vi" Type="VI" URL="../Knock Sensor 1.0 Run - Multi FPGA.vi"/>
<Item Name="Knock Sensor 1.0 Write Inputs.vi" Type="VI" URL="../Knock Sensor 1.0 Write Inputs.vi"/>
</Item>
</Item>
Expand All @@ -177,6 +212,7 @@
<Item Name="Status Run.vi" Type="VI" URL="../Status Run.vi"/>
</Item>
<Item Name="Types" Type="Folder">
<Item Name="FPGA Master ref.ctl" Type="VI" URL="../FPGA Master ref.ctl"/>
<Item Name="FPGA Refs.ctl" Type="VI" URL="../FPGA Refs.ctl"/>
<Item Name="RT Data.ctl" Type="VI" URL="../RT Data.ctl"/>
</Item>
Expand All @@ -192,6 +228,7 @@
<Item Name="Execute Engine - Multi FPGA.vi" Type="VI" URL="../Execute Engine - Multi FPGA.vi"/>
<Item Name="Execute Engine Wrapper.vi" Type="VI" URL="../Execute Engine Wrapper.vi"/>
<Item Name="Init Unused IP.vi" Type="VI" URL="../Init Unused IP.vi"/>
<Item Name="Init Unused IP - Multi FPGA.vi" Type="VI" URL="../Init Unused IP - Multi FPGA.vi"/>
<Item Name="Initialize Engine - Multi FPGA.vi" Type="VI" URL="../Initialize Engine - Multi FPGA.vi"/>
<Item Name="Initialize Engine - Single FPGA.vi" Type="VI" URL="../Initialize Engine - Single FPGA.vi"/>
<Item Name="Initialize ESTE.vi" Type="VI" URL="../Initialize ESTE.vi"/>
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