[top/pinout] Update from Bronze to Silver pinout status #5933
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msfschaffner
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msfschaffner
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Apr 9, 2021
| assign spi_device_sck = spi_if.sck; | ||
| assign spi_device_csb = spi_if.csb; | ||
| assign spi_device_sdi_i = spi_if.sio[0]; | ||
| assign spi_if.sio[1] = spi_device_sdo_o; |
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@sriyerg @cindychip @weicaiyang
In the ASIC pinout, the JTAG is mapped to a different position, hence we can get rid of this SPI/JTAG multiplexing here.
We still need to be able to select the right JTAG TAP, hence I have introduced the strap pin interfaces above.
tjaychen
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Apr 9, 2021
| set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { IOB7 }]; #IO_L16N_T2_13 Sch=led[5] | ||
| set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { IOB8 }]; #IO_L16P_T2_13 Sch=led[6] | ||
| set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { IOB9 }]; #IO_L5P_T0_13 Sch=led[7] | ||
| set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { IOA8 }]; #IO_L15P_T2_DQS_13 Sch=led[0] |
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dumb question, i haven't looked at the nexysvideo datasheet in awhile, but do we not have enough spare pins to populate the IORs for example?
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I haven't either, but from what I remember, the limiting factor is not the amount of available IOs of that FPGA device, but the useful header locations...
tjaychen
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Apr 9, 2021
Signed-off-by: Michael Schaffner <[email protected]>
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Latest force push squashes all commits. |
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This updates the pinout to the latest version for silver.
The PR is WIP and depends on #5793, #5928, and #5934 which will be rebased away.Only the last three commits are relevant in this PR.This has been rebased now.