[sram_ctrl,dv] Add cov exclusion for tlul_lc_gate #25731
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Excluding as we cannot reach the else condition in this module. Detailed description is available in the .el file. Signed-off-by: Pascal Nasahl <[email protected]>
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rswarbrick
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Dec 28, 2024
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I'm really sorry but I'm not really convinced by this reasoning. I was trying to write up another version of the same thing and I think the coverage item might be attainable. I'm not convinced it's worth caring about, but...
My notes:
// The condition we are excluding here is when outstanding_txn is nonzero when passing through the
// StErrorOutstanding state.
//
// For this to happen, we'd need to have an incomplete TL transaction pending (where the A side had
// happened but not the D side) when the gate became enabled, caused by the lc_en_i becoming On.
//
// The FSM state comes out of reset as StError but the lc_en_i signal is On at reset in sram_ctrl,
// so the FSM will follow the states StError (cycle 0), StErrorOutstanding (cycle 1), StActive
// (cycle 2). It *is* theoretically possible for a transaction to be enqueued in cycle zero because
// the TL inputs are top-level ports.
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Excluding as we cannot reach the else condition in this module. Detailed description is available in the .el file.