[sram_ctrl,dv] Add cov exclusion for tlul_lc_gate

Excluding as we cannot reach the else condition in this module.
Detailed description is available in the .el file.

Signed-off-by: Pascal Nasahl <[email protected]>

hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el

@@ -23,6 +23,35 @@ Transition StFlush->StActive "76->289"
 Transition StFlush->StError "76->186"
 Transition StOutstanding->StFlush "231->76"
 
+
+// There are two possible ways of entering the StErrorOutstanding state:
+// - (1) When the lc_en_i signal gets invalid, we follow StActive -> StOutstanding -> StError. We
+//       only can escape the StError when the lc_en_i signal gets valid.
+// - (2) The reset default state of this FSM is StError. When the lc_en_i signal gets valid, we
+//       enter the StErrorOutstanding state.
+//
+// (1) cannot happen in the sram_ctrl module as in this module lc_en_i is driven by the local
+// escalation register:
+// ```
+// assign lc_tlul_gate_en = lc_tx_inv(lc_tx_or_hi(escalate_en[1],
+//                                                lc_tx_bool_to_lc_tx(local_esc_reg));
+// ```
+// As this register cannot be reset, and it is connected with escalte_en, lc_tlul_gate_en == lc_en_i
+// stays always invalid once it has been invalidated.
+//
+// (2) can happen. However, landing in the else branch of this condition we are excluding here:
+// ```
+// if (outstanding_txn == '0) begin
+//   state_d = StActive;
+// end
+// ```
+// is impossible as the lc_en_i reset value is true. After reset, we immediately enter
+// StError -> StErrorOutstanding in the second clock cycle. Hence, we would need to have an
+// incoming TL-UL request at this clock cycle.
+CHECKSUM: "998580748 3219254590"
+INSTANCE: tb.dut.u_tlul_lc_gate
+Branch 2 "1850090820" "state_q" (12) "state_q StErrorOutstanding ,-,-,-,-,-,-,0"
+
 // The following exclusions were generated by UNR.
 CHECKSUM: "3523621980"
 ANNOTATION: "[UNR] all inputs are constant"