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[aes/sw] Load all-zero vector into PRNG buffer stage for masking off #22930
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The input masks are now taken from the PRNG buffer stage. This means after loading the magic seed into the PRNG and having the PRNG output the all-zero vector, the buffer stage needs to be updated as well. This can be achieved by triggering via a clearing operation of the data output registers. This resolves lowRISC#22917. Signed-off-by: Pirmin Vogel <[email protected]>
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Thanks, LGTM!
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Looks sensible, with a question about aes_serial.c
} | ||
#endif | ||
CHECK_DIF_OK(dif_aes_trigger(&aes, kDifAesTriggerDataOutClear)); |
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I notice that the equivalent line in aes_sca.c
is skipped for EnglishBreakfast. Is putting this line outside of the if/endif intentional?
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Yes it is. Only aes_serial.c
runs on English Breakfast (where we use a different way to 0 masks because there is no CSRNG). aes_sca.c
only runs on the actual chip and the CW310/340 (because English Breakfast has just 1 UART whereas the uJSON communication needs 2 UARTs).
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LGTM :) Thank you!
Thanks for your reviews. There are some CI FPGA failures but this is all spurious. The code in this PR is NOT run on the FPGA in any form in CI. I am thus merging this. |
The input masks are now taken from the PRNG buffer stage. This means after loading the magic seed into the PRNG and having the PRNG output the all-zero vector, the buffer stage needs to be updated as well. This can be achieved by triggering via a clearing operation of the data output registers.
This resolves #22917.