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[Verilator] AST not instantiated in chip_earlgrey_verilator #6656

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sriyerg opened this issue May 21, 2021 · 3 comments
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[Verilator] AST not instantiated in chip_earlgrey_verilator #6656

sriyerg opened this issue May 21, 2021 · 3 comments
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Component:RTL Priority:P2 Priority: medium Type:Question Questions
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Discrete: M3

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@sriyerg
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sriyerg commented May 21, 2021

This is probably already known, but filing an issue nevertheless because it impacts what tests can be run on Verilator. For example, pwrmgr relies on interactions with AST to get into low power mode. Hopefully we can use this to document a path forward.
sriyerg pushed a commit to sriyerg/opentitan that referenced this issue May 21, 2021
[dvsim] Fix verilator tests on DVSim
cc06f04 
- For bootrom, use the `.scr.40.vmem` image.
- Update / add other test entries
- Increase wakeup threshold for pwrmgr test
- Add pwrmgr test to DVSim as well as pytest versions of running
Verilator sims.
  - It does not work on Verilator yet due to lowRISC#6656, so its commented
  out.

Signed-off-by: Srikrishna Iyer <[email protected]>
@sriyerg sriyerg mentioned this issue May 21, 2021
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sriyerg pushed a commit that referenced this issue May 21, 2021
@sriyerg
[dvsim] Fix verilator tests on DVSim
849fd73 
- For bootrom, use the `.scr.40.vmem` image.
- Update / add other test entries
- Increase wakeup threshold for pwrmgr test
- Add pwrmgr test to DVSim as well as pytest versions of running
Verilator sims.
  - It does not work on Verilator yet due to #6656, so its commented
  out.

Signed-off-by: Srikrishna Iyer <[email protected]>
@msfschaffner
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Yes this is a known issue.
The Verilator TB is not fully aligned with the ASIC TB environment.
See also:

@tjaychen
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this one should be working for now.
I added some minor fixes in the tb such that pwrmgr can go into sleep and power up (needed for another test on verilator).
The underlying issue still isn't solved, but pwrmgr_smoke can at least run.

@tjaychen tjaychen added this to the Project: M3 milestone May 11, 2022
@tjaychen
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since ast is now already part of chip_earlgrey_verilator, i think this can be closed down.
There are separate issues tracking the convergence of the chip level template to support asic / fpga / verilator.

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@tjaychen @msfschaffner @sriyerg