[Verilator] Split top_*_verilator into testbench and chip-level module

[msfschaffner]

Split out from #5221.

• Split the Verilator top into a Verilator chip-level module (with padring and etc.) and a separate Verilator testbench. ([top] Part one of verilator refactoring #7544)
• Template the Verilator chip-level module
• Re-enable Verilator JTAG DPI

[GregAC]

@msfschaffner any idea what became of this?

[tjaychen]

the status is still the same as the last update.
We managed to split the "chip" portion from the "tb" portion, but the re-templating needed inside chiplevel.sv.top has still not been done.

[msfschaffner]

@tjaychen do we want to take another stab at this? The biggest issue here is probably how the verilator TB currently handles tristate drivers. It pulls out the in/out/oe signals explicitly into the DPI, likely due to limitations in Verilator's tristate modeling. So this may cause issues with the padring, and may require to breakout more signals at the chip boundary than just the pad signals themselves.

[tjaychen]

i was wondering about this.. it's not super clear to me how the verilator stuff is going to evolve for separate tops.
I guess my feeling was that this is closer to clean-up than a requirement, but let me know what you think. I need to examine again what other differences there are.

[a-will]

@tjaychen do we want to take another stab at this? The biggest issue here is probably how the verilator TB currently handles tristate drivers. It pulls out the in/out/oe signals explicitly into the DPI, likely due to limitations in Verilator's tristate modeling. So this may cause issues with the padring, and may require to breakout more signals at the chip boundary than just the pad signals themselves.

We may want to take another look at Verilator's capabilities in more recent versions as well. Antmicro has been bringing a lot of enhancements. :)

[msfschaffner]

Ok then P3 sounds right then. I'll unassign us for now, since we are not actively working on it.

[msfschaffner]

We potentially want to align the verilator TB for PROD to ease SW development.