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feat: bitVec shiftLeft recurrences for bitblasting #4571

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merged 51 commits into from
Jul 27, 2024

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@bollu bollu commented Jun 27, 2024

@[simp]
theorem shiftLeftRec_zero (x : BitVec w₁) (y : BitVec w₂) :
    shiftLeftRec x y 0 = x <<< (y &&& twoPow w₂ 0)  := by
  simp [shiftLeftRec]

@[simp]
theorem shiftLeftRec_succ (x : BitVec w₁) (y : BitVec w₂) :
    shiftLeftRec x y (n + 1) =
      (shiftLeftRec x y n) <<< (y &&& twoPow w₂ (n + 1)) := by
  simp [shiftLeftRec]

theorem shiftLeftRec_eq (x : BitVec w₁) (y : BitVec w₂) (n : Nat) (hn : n + 1 ≤ w₂) :
  shiftLeftRec x y n = x <<< (y.truncate (n + 1)).zeroExtend w₂ := by

These theorems are used for bitblasting shiftLeft in LeanSAT.

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leanprover-community-mathlib4-bot commented Jun 27, 2024

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@bollu bollu force-pushed the upstream-shiftLeft-recurrence branch from f16515b to 640df34 Compare July 3, 2024 07:17
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@kim-em kim-em added the awaiting-author Waiting for PR author to address issues label Jul 8, 2024
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bollu commented Jul 25, 2024

awaiting-review

@github-actions github-actions bot added awaiting-review Waiting for someone to review the PR and removed awaiting-author Waiting for PR author to address issues labels Jul 25, 2024
/--
If `x &&& y = 0`, then addition does not overflow, and thus `(x + y).toNat = x.toNat + y.toNat`.
-/
theorem toNat_add_eq_toNat_add_toNat_of_and_eq_zero {x y : BitVec w} (h : x &&& y = 0#w) :
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toNat_add_of_and_eq_zero will suffice: if there's only one sensible RHS, it doesn't need to be described in the name.

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kim-em commented Jul 26, 2024

Besides the renamings, and Alex's comment suggestion this now looks good to go!

@kim-em kim-em added this pull request to the merge queue Jul 27, 2024
Merged via the queue into leanprover:master with commit bb9c9bd Jul 27, 2024
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github-merge-queue bot pushed a commit that referenced this pull request Aug 7, 2024
We follow the same strategy as
#4872,
#4571, and implement bitblasting
theorems for `sshiftRight`.

---------

Co-authored-by: Tobias Grosser <[email protected]>
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