main_to_vhdlprimitive

myown_i2c/my_i2c_fsm.vhd

@@ -71,7 +71,7 @@ architecture Behavioral of my_i2c_fsm is
 
 	type clock_mode is (c0,c1,c2,c3);
 	signal c_cmode0,n_cmode0 : clock_mode;
-	signal c_cmode0_rc1 : std_logic;
+	signal c_cmode0_rc_clock : std_logic;
 
 	component ripple_counter is
 	Generic (
@@ -87,25 +87,57 @@ architecture Behavioral of my_i2c_fsm is
 	o_ping : out std_logic
 	);
 	end component ripple_counter;
-	constant RC_N : integer := 4;
-	constant RC_MAX : integer := G_BYTE_SIZE;
+	constant RC0_N : integer := 4;
+	constant RC0_MAX : integer := G_SLAVE_ADDRESS_SIZE*2;
+	signal rc0_cpb,rc0_mrb : std_logic;
+	signal rc0_q : std_logic_vector(RC0_N-1 downto 0);
+	signal rc0_ping : std_logic;
+	constant RC1_N : integer := 4;
+	constant RC1_MAX : integer := G_BYTE_SIZE;
 	signal rc1_cpb,rc1_mrb : std_logic;
-	signal rc1_q : std_logic_vector(RC_N-1 downto 0);
+	signal rc1_q : std_logic_vector(RC1_N-1 downto 0);
 	signal rc1_ping : std_logic;
+	constant RC2_N : integer := 2;
+	constant RC2_MAX : integer := 2;
+	signal rc2_cpb,rc2_mrb : std_logic;
+	signal rc2_q : std_logic_vector(RC2_N-1 downto 0);
+	signal rc2_ping : std_logic;
 
 begin
 
+	entity_rc0 : ripple_counter
+	Generic map (N => RC0_N, MAX => RC0_MAX)
+	Port map (
+	i_clock => c_cmode0_rc_clock,
+	i_cpb => rc0_cpb,
+	i_mrb => rc0_mrb,
+	i_ud => '1',
+	o_q => rc0_q,
+	o_ping => rc0_ping
+	);
+
 	entity_rc1 : ripple_counter
-	Generic map (N => RC_N, MAX => RC_MAX)
+	Generic map (N => RC1_N, MAX => RC1_MAX)
 	Port map (
-	i_clock => c_cmode0_rc1,
+	i_clock => c_cmode0_rc_clock,
 	i_cpb => rc1_cpb,
 	i_mrb => rc1_mrb,
 	i_ud => '1',
 	o_q => rc1_q,
 	o_ping => rc1_ping
 	);
 
+	entity_rc2 : ripple_counter
+	Generic map (N => RC2_N, MAX => RC2_MAX)
+	Port map (
+	i_clock => c_cmode0_rc_clock,
+	i_cpb => rc2_cpb,
+	i_mrb => rc2_mrb,
+	i_ud => '1',
+	o_q => rc2_q,
+	o_ping => rc2_ping
+	);
+
 	i2c_clock_process : process (i_clock) is
 		constant I2C_COUNTER_MAX : integer := (BOARD_CLOCK / BUS_CLOCK) / 4;
 		variable count : integer range 0 to (I2C_COUNTER_MAX*4)-1;
@@ -141,16 +173,16 @@ begin
 		case c_cmode0 is
 			when c0 =>
 				n_cmode0 <= c1;
-				c_cmode0_rc1 <= '1';
+				c_cmode0_rc_clock <= '1';
 			when c1 =>
 				n_cmode0 <= c2;
-				c_cmode0_rc1 <= '0';
+				c_cmode0_rc_clock <= '0';
 			when c2 =>
 				n_cmode0 <= c3;
-				c_cmode0_rc1 <= '0';
+				c_cmode0_rc_clock <= '0';
 			when c3 =>
 				n_cmode0 <= c0;
-				c_cmode0_rc1 <= '0';
+				c_cmode0_rc_clock <= '0';
 		end case;
 	end process clock_mode_0_com;
 
@@ -166,21 +198,18 @@ begin
 	end process p2;
 
 	i2c_send_sequence_fsm : process (c_state,c_cmode0,i_enable,i_slave_address,i_bytes_to_send) is
-		constant SLAVE_INDEX_MAX : integer := G_SLAVE_ADDRESS_SIZE;
-		constant SDA_WIDTH_MAX : integer := 2;
-		variable data_index : std_logic_vector(G_BYTE_SIZE-1 downto 0);
-		variable slave_index : integer range 0 to SLAVE_INDEX_MAX-1;
-		variable sda_width: integer range 0 to SDA_WIDTH_MAX-1;
 		variable vtemp_sda,vtemp_sck : std_logic;
 	begin
 		n_state <= c_state;
 		case c_state is
 			when idle =>
-				slave_index := 0;
+				rc0_mrb <= '1';
 				rc1_mrb <= '1';
+				rc2_mrb <= '1';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
+				rc2_cpb <= '0';
 				o_busy <= '0';
-				sda_width := 0;
 				vtemp_sda := '1';
 				vtemp_sck := '1';
 				if (i_enable = '1') then
@@ -189,10 +218,12 @@ begin
 					n_state <= idle;
 				end if;
 			when sda_start =>
-				slave_index := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
-				sda_width := 0;
+				rc2_cpb <= '0';
 				if (c_cmode0 = c0) then
 					vtemp_sck := '1';
 					vtemp_sda := '1';
@@ -203,10 +234,12 @@ begin
 				end if;
 				o_busy <= '1';
 			when start =>
-				slave_index := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
-				sda_width := 0;
+				rc2_cpb <= '0';
 				if (c_cmode0 = c0) then
 					vtemp_sda := '0';
 					vtemp_sck := '1';
@@ -216,55 +249,58 @@ begin
 					vtemp_sck := vtemp_sck;
 				end if;
 				o_busy <= '1';
-				vtemp_sda := vtemp_sda;
-				vtemp_sck := vtemp_sck;
 			when slave_address =>
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '1';
 				rc1_cpb <= '0';
+				rc2_cpb <= '0';
 				o_busy <= '1';
-				sda_width := 0;
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
 				end if;
 				if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
 					vtemp_sck := '1';
 				end if;
-				if (slave_index /= SLAVE_INDEX_MAX-1) then
+				if (to_integer(unsigned(rc0_q)) = G_SLAVE_ADDRESS_SIZE-1) then
+					n_state <= slave_address_lastbit;
+				else
 					if (c_cmode0 = c0) then
-						vtemp_sda := i_slave_address(slave_index);
-						slave_index := slave_index + 1;
+						vtemp_sda := i_slave_address(to_integer(unsigned(rc0_q)));
 						n_state <= slave_address;
 					else
-						vtemp_sda := vtemp_sda;
-						vtemp_sck := vtemp_sck;
+						n_state <= slave_address;
 					end if;
-				else
-					n_state <= slave_address_lastbit;
 				end if;
 			when slave_address_lastbit =>
-				slave_index := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
+				rc2_cpb <= '0';
 				o_busy <= '1';
-				sda_width := 0;
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
 				end if;
 				if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
 					vtemp_sck := '1';
 				end if;
 				if (c_cmode0 = c0) then
-					vtemp_sda := i_slave_address(SLAVE_INDEX_MAX-1);
+					vtemp_sda := i_slave_address(G_SLAVE_ADDRESS_SIZE-1);
 					n_state <= slave_rw;
 				end if;
 				vtemp_sda := vtemp_sda;
 				vtemp_sck := vtemp_sck;
 			when slave_rw =>
-				slave_index := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
+				rc2_cpb <= '0';
 				o_busy <= '1';
-				sda_width := 0;
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
 				end if;
@@ -279,11 +315,13 @@ begin
 					vtemp_sck := vtemp_sck;
 				end if;
 			when slave_ack =>
-				slave_index := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
+				rc2_cpb <= '0';
 				o_busy <= '1';
-				sda_width := 0;
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
 				end if;
@@ -297,10 +335,12 @@ begin
 				vtemp_sda := vtemp_sda;
 				vtemp_sck := vtemp_sck;
 			when data =>
-				sda_width := 0;
-				slave_index := 0;
-				rc1_cpb <= '1';
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
+				rc1_cpb <= '1';
+				rc2_cpb <= '0';
 				o_busy <= '1';
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
@@ -321,69 +361,70 @@ begin
 				end if;
 			when data_ack =>
 				o_busy <= '1';
-				slave_index := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
+				rc2_cpb <= '1';
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
 				end if;
 				if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
 					vtemp_sck := '1';
 				end if;
 				if (c_cmode0 = c0) then
-					vtemp_sda := '0';
-					if (sda_width = SDA_WIDTH_MAX-1) then -- XXX latch
-						sda_width := 0;
+					vtemp_sda := '1';
+				end if;
+					if (to_integer(unsigned(rc2_q)) = RC2_MAX-1) then
 						if (i_enable = '1') then
 							n_state <= data;
-							sda_width := 0;
 						else
 							n_state <= stop;
-							sda_width := 0;
 						end if;
 					else
-						sda_width := sda_width + 1;
 						n_state <= data_ack;
 					end if;
-					sda_width := sda_width;
-				end if;
 				vtemp_sda := vtemp_sda;
 				vtemp_sck := vtemp_sck;
 			when stop =>
 				o_busy <= '1';
-				slave_index := 0;
-				sda_width := 0;
+				rc0_mrb <= '0';
 				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
+				rc2_cpb <= '0';
 				if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
 					vtemp_sck := '0';
 				end if;
 				if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
 					vtemp_sck := '1';
 				end if;
-				vtemp_sda := '0';
-				n_state <= sda_stop;
-			when sda_stop =>
-				sda_width := 0;
-				rc1_mrb <= '0';
-				rc1_cpb <= '0';
 				if (c_cmode0 = c0) then
-					n_state <= idle;
-				else
+					vtemp_sda := '0';
 					n_state <= sda_stop;
-					vtemp_sck := '1';
-					vtemp_sda := '1';
 				end if;
-				slave_index := 0;
+			when sda_stop =>
+				rc0_mrb <= '0';
+				rc1_mrb <= '0';
+				rc2_mrb <= '0';
+				rc0_cpb <= '0';
+				rc1_cpb <= '0';
+				rc2_cpb <= '0';
+				n_state <= idle;
+				vtemp_sck := '1';
+				vtemp_sda := '0';
 				o_busy <= '1';
 			when others =>
---				vtemp_sda := vtemp_sda;
---				vtemp_sck := vtemp_sck;
-				o_busy <= '0';
-				rc1_mrb <= '0';
+				n_state <= idle;
+				rc0_mrb <= '1';
+				rc1_mrb <= '1';
+				rc2_mrb <= '1';
+				rc0_cpb <= '0';
 				rc1_cpb <= '0';
-				sda_width := 0;
-				slave_index := 0;
+				rc2_cpb <= '0';
+				o_busy <= '0';
 		end case;
 		temp_sda <= vtemp_sda;
 		temp_sck <= vtemp_sck;