main_to_vhdlprimitive #2
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…op condition looks ok my_i2c_fsm_combinational - remove rc latches,i2c timings and start/stop condition looks ok
my_i2c_fsm_combinational - wip - sdasck latches,rename
my_i2c_fsm_combinational - wip - sdasck latches my_i2c_fsm_combinational - wip - sdasck latches
…names my_i2c_fsm_combinational - wip - test_oled_fsm remove some latches,renames
my_i2c_fsm_combinational - wip - adjust glcdfont
… version,use test_oled seq module
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