[SYCL-PTX] Enable half for CUDA target. #2003
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@Naghasan, it looks like two SYCL tests should be updated.
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This patch enables 16 bits float in the libclc. It also provides a better builtins binding (SPIRVBuiltins.td) for __fp16 (with native halfs) and _Float16. It will now depends on the programing mode enabled. Signed-off-by: Victor Lomuller <[email protected]>
Rather that using a bit filed to mark whether a QualType is directly accessed or produced by a function, the functionality now uses subclass. Signed-off-by: Victor Lomuller <[email protected]>
Signed-off-by: Victor Lomuller <[email protected]>
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Handle the case when we have `DebugInfoNone` for the Text argument which is usually expected to be `OpString`. Original commit: KhronosGroup/SPIRV-LLVM-Translator@bde3b51
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This patch enables 16 bits float in the libclc.
It also provides a better builtins binding (SPIRVBuiltins.td) for __fp16 (with native halfs) and _Float16.
It will now depends on the programing mode enabled.
Note: due to #1814, we have to disable a test as a work around.
Signed-off-by: Victor Lomuller [email protected]